DS90UB949A-Q1: Pattern Generation with Spread Spectrum

Hi Hirata-san,

You can generate the pattern with different type of timing mode such as external, internal, or internal timing with external clock. Yes you may provide an external clock with SSC enabled. The pattern generator doesn't related to SSC. It can generate the pattern without SSC.

Hope this helps. Let me know if you have any questions.

Aaron

Hi Aaron-san,

Thanks for your answer.

Is my understanding below correct?

external timing mode

internal timing mode

internal timing with external clock

So do you mean we can apply the clock with SSC to the X1 but it does not affect the pattern generator and pattern generator is without SSC in any case?

I appreciate your support.

Regards,

Hirata

Hi Hirata-san,

The second diagram is internal timing mode with internal clocking. It does, but not directly. The internal timing block uses the external clock to generate a specific timing for the patgen.

Aaron

Hello Aaron-san,

Sorry but I do not understand well, sorry...

What is the configuration for 3 method and differences?

if using internal timing with external clock with SSC, the pattern will be SSC modulated? How to set each setting respectively?

Thanks for your support.

Regards,

Hirata

Hi Hirata-san,

Sorry for the confusion. I thought you already layouted the three method in your diagrams. I just want to clarify on the second diagram is using internal clocking.

Yes when you use external clock with SSC then everything in the circuit will be modulated. As far as I remember, there is no register setting.

Hope this helps. Let me know if you have any questions.

Aaron

Aaron-san,

I am sorry I might be confused so much but I am checking the datasheet a bit more so let me ask you again.

As I ask you in the first question, and draw the figure as below, I thought "internal timing with external clock" was based on the clock into the X1.

However is it really correct?

The description of the X1 says this is for the CEC.

There is no description of that this clock is used for FPD Link or pattern generator. 

What is the "external clock" in the below highlighted portion?

Is it the clock into the X1?

Or Is it the IN_CLK+/- (TMDS Clock)?

or any other?

To enable the "internal timing with external clock", should we set the 0x65 bit 3 and bit 2 should be 1?

You said there is no register settings but is it really correct?

Is below portion in this document is the settings of the "internal timing with external clock"?

http://www.ti.com/lit/pdf/SNLA132

How much we can modulate the clock signal in this case?

The SSC below is for the TMDS signal including IN_CLK+/- (TMDS Clock) or clock into the X1?

Below spec is described in electrical characteristics? (I don't find well sorry)

Thanks for your support.

Regards,

Hirata

Hi Hirata-san,

No worries. I will look into this and get back with you by 8/31.

Aaron

Hello Aaron-san,

Any feedback on this?

Regards,

Hirata

Hi Hirata-san,

I'm sorry for the delayed. I need a bit more time to review the material. I will get back with you by tomorrow or early next week.

Aaron

Hi Aaron-san,

Any feedbacks?

Regards,

Hirata

Hi Hirata-san,

Basically, you need to apply the SSC clock to the TMDS CLKIN (not the XI input). This then would modulate internal PATGEN with external clock modes or full end-end mode. The section 7.3.21 is the tolerance that the device can support. So, if you want to use SSC with 949 you also have to be able to spread the data lines in phase with the SSC clock, otherwise it is possible to get HDMI input bits mis-sampled.

Aaron

Hi Aaron-san,

Thanks for your answer.

So conclusion is, to achieve pattern generation with SSC, customer needs to input the SSC-modulated Clock with the limitation described in 7.3.21 into IN_CLK+ / IN_CLK- , right?

In case the customer tried pattern generation using "Internal timing with external clock", does they need to spread the data line (IN_D0+/-, IN_D1+/-, IN_D2+/-)? I thought data line does not affect anything when the pattern generation.

Could you also answer how to set the register as I originally asked?

Thank you.

Regards,

Hirata

Hi Hirata-san,

Yes the limitation is described in section 7.3.21. Are you referring to setting the SSC?

Aaron

Aaron-san,

Thank you for the confirmation.

I meant device register settings.

I want your answer for below.

Regards,

Hirata

Hi Hirata-san,

Yes you are correct the 0x65[3] should be set, and if you have your own timing that program into the register, you would need to set the 0x65[2] as well.

Aaron

Hi Aaron-san,

Thank you for your answer.

When customer uses the "Internal timing with external clock", could you let me know if the IN_Dx+/-, and the other HDMI pin such as RX_5V can be open?

Thanks for your support.

Regards,

Hirata

Hello Casey-san,

I understood. Thanks for your prompt answer!

Regards,

Hirata