SN75DPHY440SS: Question of I2C controlled

Jimmy

The DPHY440 local I2C interface is enabled when RSTN is input high. Access to the CSR registers is supported during ultra-low power state (ULPS). The EQ/SCL and ERC/SDA terminals are used for I2C clock and I2C data respectively.

Thanks

David

Hi David,

We appreciated your great support!

If our customer wants to use HW controlled, Can he cancel the delay time?

Thanks,

Jimmy

Jimmy

Which delay time is he referring to? Please see Figure 21, Table 18 for the timing requirement.

Thanks

David

Hi David,

We appreciated your great support!

Our question is that I control SN75DPHY440SS via HW design. Can we switch the delay time to 0?

Many Thanks,

Jimmy

Jimmy

Are you referring to the delay time between the RSTn and Power-on? No, you need to make sure the DPHY440 receives a proper reset.

Thanks

David