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DS125DF111: Receive Retimer can detect but not lock the signal,

Part Number: DS125DF111

Hello, based on the DS1125DF111 transceiver data transmission module, in the case of a direct connection with a cable, the receiving end can detect and lock the signal, but with wireless transmission, the receiving end can only detect the signal, not lock the signal, from Signal integrity analysis, where is the problem?At present, the interface is 1.25G ,I have choose MODE 0,and register 0x3A= 0xFF.

  • Hi,

    Can you provide a retimer channel registers dump for the case where the CDR lock issue is being observed?

    Thanks,

    Rodrigo Natal

  • Hi,

    The following is my register configuration table

                  TX Registrt Setting          RX Registrt Setting
    addr data mask addr data mask
    0xFF 0x05 0x0F 0xFF 0x04 0x0F
    0x00 0x04 0x04 0x00 0x04 0x04
    0x0A 0x0C 0x0C 0x0A 0x0C 0x0C
    0x60 0x00 0xFF 0x60 0x00 0xFF
    0x61 0xB2 0xFF 0x61 0xB2 0xFF
    0x62 0x80 0xFF 0x62 0x80 0xFF
    0x63 0xBE 0xFF 0x63 0xBE 0xFF
    0x64 0xCF 0xFF 0x64 0xCF 0xFF
    0x31 0x00 0x60 0x31 0x00 0x60
    0x2D 0x08 0x08 0x2D 0x08 0x08
    0x03 0x00 0xFF 0x03 0x10 0xFF
    0x3A 0x00 0xFF 0x3A 0xFF 0xFF
    0x1E 0x08 0x08 0x1E 0x08 0x08
    0x2D 0x00 0x07 0x2D 0x00 0x07
    0x56 0x0F 0x0F 0x56 0x0F 0x0F
    0x0C 0x00 0x08 0x0A 0x00 0x0C
    0x0A 0x00 0x0C

    Thanks,

    Kevin cao

  • Hi Kevin. What value is being observed on retimer channel register 0x02 when the CDR lock issue is being observed?

    Thanks,

    Rodrigo Natal

  • Hi Rodrigo, bit[3] = 1 of register 0x02 .

    Thanks,

    Kevin cao

  • I need the full register value for debug purpose; see register description below. But doesn't 0x02[3]=1 mean that the CDR is locked? If so, what is the problem then?

    Channel register 0x02 description -> CDR Status [7:0]

    Bit[7] = PPM Count met
    • 1: The data rate is within the specified PPM tolerance (typically around ±1000 ppm unless specified otherwise in Reg 0x64).
    • 0: Error: PPM tolerance exceeded.

    Bit[6] = Auto Adapt Complete
    • 1: CTLE auto-adaption is complete.
    • 0: CTLE auto-adaption in progress.

    Bit[5] = Fail Lock Check
    • 1: Signal quality and amplitude level is not sufficient for lock.
    • 0: Signal quality and amplitude level is sufficient for CDR lock.

    Bit[4] = Lock
    • When asserted, indicates CDR is locked to the incoming signal.

    Bit[3] = CDR Lock
    • When asserted, indicates CDR is locked to the incoming signal (same status as bit 4).

    Bit[2] = Single Bit Limit Reached
    • 1: Number of bit transitions to acquire CDR lock has been met.
    • 0: Not enough bit transitions within the CDR lock time window to declare lock.

    Bit[1] = Comp LPF High
    • 1: Data rate exceeds the VCO upper limit, based on loop filter comparator voltage.
    • 0 = Data rate is within VCO upper limit.

    Bit[0] = Comp LPF Low
    • 1: Data rate is below the VCO lower limit, based on loop filter comparator voltage.
    • 0 = Data rate is within VCO lower limit.

    Thanks,

    Rodrigo

  • Hi Rodrigo,

      This is the case. The above register configuration can lock the signal when using a cable connection, but when I use wireless transmission, I can only detect the signal but cannot lock the signal. I want to know where the problem is .

    Thanks,

    Kevin cao

  • Can you provide the value for the CDR status register i.e. channel register 0x02 for the wireless transmission case when CDR is locked?