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DP83826I: Datasheet errata + transformerless operation

Alecsandru Neacsu
Prodigy 190 points
Part Number: DP83826I

Hello,

I have four questions

1)

Current datasheet of DP83826 (SNLS674D) says about register LEDCFG (0x460) two things:

- at table 9.5.75: bits 15-12 are related to LED1 configuration, details are given for their possible values, but these bits are (apparently) read-only; bits 0-3 are also read-only, without any description of their value

- at figure 9.9: "controls for LED1 - LEDCFG_0x460", which means that LED1 should be configurable through this register. But this seems impossible, as bits 15-12 associated with LED1 are read-only.

Current migration document SNLA338 says also about the same register 0x460:

- at paragraph 2.6: "Program register 0x0460 with 0x0001 for the LED to stay high OR register 0x0460 with 0x0008 for a blinking LED". This is again is a contradiction: write to read-only bits, some unknown (not documented) values.

Even more, document SNLA344A again writes to read-only bits some undocumented values:

- at paragraph "LED Configuration": "Write to PHY register 0x460 value 0x0005 (100Mbit speed)"

Through trial-and-error, I arrived at the conclusion that bits 0-3 are actually read-write. More, according to my observations, bits 3-0 are related to LED1, with the meaning/details shown in the datasheet for bits 15-12. Can you confirm this?

2) Register 0x304 (table 9-79 of datasheet) seems to have a typo: line bits 5-3, column "Description", instead of the existing text "cfg_led0_gpio_ctrl[2:0]" we should read "cfg_led1_gpio_ctrl[2:0]". Can you confirm this?

3) Same register 0x304, line bits 2-0, same column: instead of "1h=reserved", maybe we should read "1h=Clock output selected by register field cfg_led1_clk_sel". Can you confirm this?

4) Could you clarify some aspects related to register 0x404? I imagine that this register can enable "full MLT3", i.e. linear output stage (Class A) where each single-ended signal is MLT3 (has three voltage levels), not just the differential pair. This would be the opposite of the default setting, which sets "reduced current" / "minimal current" MLT3, i.e. push-pull (digital) output stage (Class B) where only the difference between signals is MLT3, while each single-ended signals is digital (two states only). We need in our application that each signals is MLT3, as this method is much more robust in transformerless operation.

I have found various forum discussions on this, as well as other TI PHYs which document this register - but for DP83826 it's just "Reserved". Can you please share what to write in this register to activate  full MLT3?

Best regards,

Alecsandru

  • 0
    TI__Genius 17140 points

    Hi Alecsandru,

    We are looking into your questions and I hope to give you answers by the end of business Thursday (8/26).

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml)

  • 0 in reply to Joe Vanacore
    Prodigy 190 points

    Thanks. Meanwhile, I add here some more questions:

    5) Document SNLA344A recommends (for EtherCAT) to clear bit 0 of register 0x02D, to avoid link drop due to baseline wander. However, datasheet has no reference to this register. I am currently reading 0x0100 from this register (0x02D), i.e. bit 0 seems to be already zero. Should I take further actions?

    6) Register 0x469 (datasheet table 9-99) bits 6 (LED2_polarity) and 2 (LED1_polarity) seem to have their initial value based on strap values, as indicated by column "Type". However, paragraphs 9.4.1.1 and 9.4.1.2 show no such strap. The closest ones could be strap4 (for LED2) and strap1 (for LED1), but these straps have different purpose (PHY_ADD2, respectively speed 10M/100M).  Please clarify.

    7) Table 9-95 register 0x461 bit 14 seems to be read-only and reserved, however paragraph 9.3.11.6 gives an example of how to write (set) this bit, which supposedly will set MAC impedance to 99.25 ohm. But another register, 0x302 (table 9-77) seems to control the MAC impedance through it's bit 15-14 (another question: 15 or 14? ). And the value of 99.25ohms seems a little off, maybe should read as 90 ohms? So, this question 7) actually contains many (sub) questions.

    8) Crystal tolerance should be +/-50ppm or +/-100ppm? Page 9 line XI/50MHzIn states 50ppm, page 17 states 100ppm. Page 68 table 9-43 bits 1-0 explain the maximum packet size for each of the two tolerances. My question is: For short packets, less than ~1550 bytes, using a MII (4-bit) interface, is it OK to go with +/-100ppm tolerance, similar to other PHY requirements?

    9) Page 15, last line (MAC termination), should also include TX_CLK in the list of pins. Can you confirm this?

    10) Table 9-76 bit 5 column "Description" has a typo, probably should read as "...between TD+ and TD-"

    11) Page 18 first line has no info for the long-term jitter, just empty cells.

    Thanks in advance,

    Alecsandru

  • 0 in reply to Alecsandru Neacsu
    TI__Genius 17140 points

    Hi Alecsandru,

    We will look into your additional questions and I hope to give you answers to all of them by the end of business Friday (8/27).

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml)

  • 0 in reply to Joe Vanacore
    TI__Genius 17140 points

    Hi Alecsandru,

    Apologies for the delayed response. 

    Here are my responses to your questions:

    1. Here this is a mistake in the datasheet, but please test which led has what registers, to my knowledge the settings described will configure the Leds mentioned. Led LED grouping is swapped so LED1 is 3-0 LED2 is 7-4 and LED3 is 11-8 the description status the same. Please confirm with your tests.
    2. Yes this is a typo of the datasheet this register is valid for LED1_GPIO functions.
    3. Same register 0x304, line bits 2-0, same column: instead of "1h=reserved", maybe we should read "1h=Clock output selected by register field cfg_led1_clk_sel". Will update in next refresh.
    4. On DP83826, it’s full MLT3 and not reduced current. No addition setting is needed for Transformless operation.
    5. Yes this is a mistake of the document the register I am referring to us 0x000B here the bit 0 is setting the function(Drop the link based on Signal/Energy Loss indication) and need to be disabled
    6. Here is our explanation:
      1. The LED’s drivers have auto polarity detection.
      2. This is needed to multiplex the pins for strapping and LED function.
      3. For example LED_2 is : PHY Address 2 strap. If someone using the strap ( Pull -UP ) to change the PHY address 2 to 1, the PIN will needs to be pulled high through a resistors. However if connected for active Low will conflict and will cause electrical contention.  If connected for active high, then additional register configuration will be needed to change it to active low.
      4. To take of this situation, our PHYs have Auto Polarity detection mechanism,  PHY at POR/reset senses the voltage on the pin and accordingly change the polarity of LED to active high or low.
    7. Answer for Question 7: 
      1. Section 9.3.11.6 reference example was from other part and we missed to update this. Higher granularity options are not available on this part This is error and will be addressed in next revision.
      2.  0x0302 is the right configuration to update the MAC impedance on DP83826. Fast is 50 ohm+ ~25% variance, Slow, I need to check.
    8. Total ppm allowed on TX by IEEE is 100 ppm. We recommend XTAL tolerance of +/-50 ppm to take care of short and large packets both.
      1. Yes, if your use-case is limited to shorter, you can target 100 ppm ( all inclusive : temp, ageing etc)
    9. Correct. It will be added in next revision.
    1. Yes, this is typo. Thank for point it out. we will fix in next revision.
    2. It’s an empty cell. The RMS jitter is derived from phase noise jitter. We will clean it up in next revision.

    Please let me know if you need further clarification and thank you for your patience.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml)