I'm having a problem where it takes a few minutes for the DP83867CS to link up.
The circuit configuration is as follows.
・ Multiple DP83867 are mounted on our circuit board.
・ FPGA and each DP83867 are connected using SGMII.
・ Reset to each DP83867 will be released from the FPGA at the same timing.
・ DP83867 and RJ-45 are mirror-connected.
・ I use a straight cable to connect to RJ-45 of DP83867 (1) and DP83867 (2) on the circuit board.
The strap settings are listed below.
・ Auto-negotiation enabled
・ Advance ability of 10/100/1000
・ Port mirroring strapped to enable
・ SGMII strapped to enable
The problem is that if I unreset with the cable connected, it takes a few minutes for the DP83867 to link up.
After the DP83867 links up, it links up as soon as I unplug and plug it in.
The registers when DP83867 is not linked up are as follows.
・ Auto-Negotiation Link Partner Ability Register (ANLPAR), Address 0x0005
→ It is 0xC1E1 and the advertisement seems to be completed.
・ PHY Status Register (PHYSTS), Address 0x0011
→ 0x1000 and 0x1300 are repeated alternately.
→ When DP83867 is linked up, it will be 0xAC02.
Please give me some advice to speed up the link up.