DS90UB962-Q1: I2C delay

Ryan Wang

Part Number: DS90UB962-Q1

Dear expert,

My system is UB962+UB935 while I2C host is at UB962 side, slave is at UB935 side.

Based on "AN-2173 I2C Communication Over FPD-Link III with Bidirectional Control Channel" app notes, I2C BCCdelay is only 9us. However, the real measurement is around 100us.

For below captured signal, YELLOW is SCL captured at UB935 SCL pin, BLUE is SCL captured at UB962 SCL pin. There is 100us delay in between. Is it normal? How to optimizing it?

Both host and slave works at 400KHz. SCL_high/LOW is set to 0x32. Other I2C timing register are in default.

over 4 years ago

0 Ryan Wang over 4 years ago

TI__Expert 7425 points

BTW， BCC rate is 50MHz

0 Ben Dattilo over 4 years ago in reply to Ryan Wang

TI__Mastermind 25765 points

Hi Ryan,

What you are showing in the image is normal. Section 3 of SNLA131A may help to understand what is happening.

"When the slave receives the write/read command from the master it holds the clock line Low. During any SCL low period, the slave holds down SCL to prevent it from rising high again to delay the SCL clock rate and pause communication."

From the same document, here is a diagram of the format when writing to a remote I2C slave:

Below is this format shown in a similar way to how you are measuring it on your system. This image is from SNLA222 (this discusses DS90UB913/4 but the concept is the same):

As you can see, the 9us (in this case 12us) delay you are referring to is measured between the end of the SCL transmission, and beginning of SCL received.

Regards,

Ben Dattilo

0 Ryan Wang over 4 years ago in reply to Ben Dattilo

TI__Expert 7425 points

Ben,

Great thanks

Interface

Interface forum

DS90UB962-Q1: I2C delay