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DP83867E: SGMII reflections

Per Lenander
Prodigy 10 points
Part Number: DP83867E

Hello, we have a DP83867E connected with 4-wire SGMII to a Marvell PHY. The PHY is powered and we have access to the MDI interface and can read its registers, but we can't establish a SGMII link.

On the PHY->Marvell side, the SGMII signal quality looks as expected. On the Marvell->PHY side, there are massive reflections, see image.

There are no strap resistors on the SGMII_SIN/P or SGMII_SON/P signals. Each differential wire has a 0.1uF capacitor in series (placed next to the PHY on the offending line). The differential signal is routed with 100 Ohm impedance, following the guidelines in the DP83867E SGMII troubleshooting guide.

When measured without the PHY (removed the capacitors and replaced with a 100Ohm termination resistor), the signal from the Marvell PHY all the way up to the capacitor pads next to the PHY was of good quality.

Any suggestions on how to continue debugging? Any register values that could be of use?

  • 0
    Prodigy 10 points

    Additional info: the LED0 strap is set to MODE2: SGMII enabled.

  • 0 in reply to Per Lenander
    TI__Genius 17360 points

    Hello,

    I have a follow-up question.

    Are you also seeing these reflections on the DP83867E side as well?

    I am a little confused by these sentences in your post:

    "On the PHY->Marvell side, the SGMII signal quality looks as expected. On the Marvell->PHY side, there are massive reflections, see image."

    Are you seeing reflections or good signal quality on the Marvell side?

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml)

  • 0 in reply to Joe Vanacore
    Prodigy 10 points

    Hello, the reflections are seen on the SGMII pair going from the Marvell to the PHY (SGMII_SIN, SGMII_SIP). The reflections are not seen on the pair leading from the PHY (SGMII_SON, SGMII_SOP), the signal quality is good there.

  • 0
    Prodigy 10 points

    We activated the MII loopback mode by performing the following operations according to the troubleshooting guide, performing these steps for 1G SGMII:

    1. Write 0x8000 to PHY register 0x1f (software reset)
    2. Write 0x4140 to PHY register 0x00 (MII Loopback mode + 1G fixed speed, auto-neg off)
    3. Write 0x4000 to PHY register 0x1f (software restart)

    We measured the SGMII signals on the caps for Switch->PHY (top trace) and on the caps for PHY->Switch (bottom trace, looped back):

    As mentioned in the opening text, we have tried removing the caps on the Switch->PHY pair and terminating with 100 Ohm, and the signal looks fine then. There is only a few millimeters on the other side of the caps before the traces connect to the PHY SGMII_SIN/P pins.

  • 0 in reply to Per Lenander
    TI__Genius 17360 points

    Hello,

    I have reached out to the rest of the team and we are looking into your question. I hope to provide you feedback by the end of business Wednesday (9/1).

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml)

  • 0 in reply to Joe Vanacore
    Prodigy 10 points

    Hello Joe, have you had time to get feedback on this issue?

  • 0 in reply to Per Lenander
    TI__Genius 17360 points

    Hello,

    Apologies for the delay. 

    Here is my feedback:

    Have you tried unidirectional data transfer?

    I would also like to know the values in register 0x0037 to see if SGMII Auto-Negotiation completed.

    Can you please also try setting the SGMII_AUTONEG_TIMER to '00b'? This will correspond to a 16ms Auto-Negotiation timer for SGMII.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml)

  • 0 in reply to Joe Vanacore
    Prodigy 10 points

    Hello, thank you for the reply.

    This is the value of the 0x37 status register:

    > smi write 1 1 0xd 0x1f
    Write-SMI busId 1, phyAddr 1, regAddr 13, val 0x1f: ok
    > smi write 1 1 0xe 0x37
    Write-SMI busId 1, phyAddr 1, regAddr 14, val 0x37: ok
    > smi write 1 1 0xd 0x401f
    Write-SMI busId 1, phyAddr 1, regAddr 13, val 0x401f: ok
    > smi read 1 1 0xe
    Read-SMI busId 1, phyAddr 1, regAddr 14: 0x3

    The indication is that the PHY thinks it has completed auto-negotiation. The MAC side doesn't agree.

    I tried changing the specified field in register 0x31, with no discernable difference.

    Would it be a viable path forward to turn off autonegotiation and specify a fixed configuration? If so, what would be the correct bits to set for 1G Full Duplex?

  • 0 in reply to Per Lenander
    TI__Genius 17360 points

    Hello,

    Please have a look at register 0x0000. You will be able to set the DP83867E to 1G full-duplex with auto-negotiation disabled in this register.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml)

  • 0 in reply to Joe Vanacore
    Prodigy 10 points

    Hello! Thank you for the help with debugging. More than likely there are a number of external factors that led to the issues, and ultimately we will make a new board revision to address some of them. For the time being, this issue can be closed. I will post again if the new revision has similar reflection issues that we cannot explain.