10M-50M bite rate RS485 transceiver with FAST idle bus failsafe detection

Danilo,

The most recently released 10M-50Mbps RS-485 transceivers are: THVD1550, THVD1450, THVD1520, THVD1450, and THVD1429. BTW, this e2e post has detailed information about more new devices.

You're correct about the failsafe feature of TI devices - it's for detecting fault conditions (open, idle, short) and generating a constant high at R (pin 1). This app note discusses the detail. Basically most of the devices listed above have the same mechanism (-20mV to -200mV RX Vith). 

Could you elaborate the purpose of FAST idle detection in your application? How fast do you want the response time to be? Actually the receiver propagation delay could be in hundreds of ns. I think the time constraint is more on input (bus) signal than the device's operation.  

Regards,

Hi Hao,

Thank you for your response. According to our customer,

First of all, I would like to get some things clear (to me). 

Since I do not find failsafe switching characteristic information from your data sheets (only exception is 65HVD2x which showed 250 us), I actually don’t know how fast your device failsafe signal switch, but I notice that most of Maxim’s devices are switching at 10us, so I subjectively assuming your devices also at around several micro seconds.

Now, at this opportunity, it will be great if you could get me clear on below questions:

1. What are your device failsafe signal switching characteristic, especially idle bus signal?  I know that from last driving transmitter stop driving to each node’s receiver input signal settled down there is bus propagation time, what I am talking about is switching time from receiver input signal reach failsafe threshold to receiver’s output.
2. Do you add any delay time in between receiver’s input and its output of failsafe signal chain?  I am sure Maxim do add such delay as no IC has such slow characteristic unless a big RC circuit added internally. 
3. According to your receiver’s internal biasing circuit (as 65HVD1176 as attached),  when idle bus, receiver differential input (VA-VB) should be between 1mV and 30-50mV depending on how many nodes (same receivers) connected on bus. This idle bus receiver input is well above your VTH+ threshold (usually -20mV), so theoretically your receiver would yield logic high output after normal circuit propagation if no delay circuit added (this is like bus is driven by internal biasing circuit of all nodes’ receivers).  My question is,   Do you have separate failsafe detection circuit some thing like when input between 200mV and -200mV a delay is added, when input > +200mV or > -200mV straight going without a delay added?   in case a delay circuit is added, what is receiver logic output during the delay time? 

Just for your information,  Maxim has an interesting talk about parallel failsafe circuit at https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3662.html 

Now, back to your question.

As we all know, RS485 is a physical layer specification only,  on top of RS485, system designers are free to design and implement their own data link layer protocol scheme based on specific application needs. Profibus has done a good example for industrial process application. While I am looking into a possibility of using RS485 for certain high speed demanding application such as robotics industry.

In typical multipoint RS485 network, any node wanting to send data must be sure last sending node driver on bus has been disabled, two way of being sure of this, one is to use start/stop bit or byte, another way is to rely on and monitoring bus idle signal. 

Considering bus idle as fail and combining with bus open/short together as failsafe signal and output at receiver data channel concept seems coming from Profibus,  I don’t know why a delay time is added/required for so called “failsafe” signal,  but I remember Profibus using start/stop bit and do not use bus idle signal for bus drivers hand over purpose.   

Anyway, I have hard time to figure out why all venders have added delay time at failsafe signal.

In my point of view:

First, as RS485 transceiver manufacturer, a natural/original bus idle signal without any delay added should be designed at least keep it as a variant rather than all products follow the same rule.  I know Profibus has significant market share of RS485 transceiver, but by adding delay to all devices, venders are taking away system designer’s freedom of exploring other application and forcing people to stick on Profibus.  This will restrict/limit venders own business opportunities too.

Second, for a 50-100Mbs kind of data rate transceiver,  micro seconds level delay is too long to be considered acceptable, because several micro seconds is the time of completely sending a message, a high speed data link layer protocol will not tolerate micro seconds level of delay on physical layer, especially a man-made delay.

Third,  a demand for extender/repeater also require a receiver with fast bus idle signal. Imagine that in my environment a 50Mbs data rate bus only good for 30 meters, but my application require 60 meters communication, what I can do is to separate 60 meters bus into two segment A and B at 30 meters of each segment, than I need to implement a physical layer extender in between A and B segment,  such extender will have to transfer bus idle signal from one segment to another in both direction without additional delay apart from cable propagation delay. 

In short, to allow system designer exploring other data link layer protocol on top of RS485, also catering for today’s 50-100Mbs data rate RS485 application, a fast (as fast as possible) bus idle signal is always expected, importantly, it will be good to have independent bus idle signal output (separating from receiver’s data output) by using 10 pin or 14 pin package. 

I hope I am clearly expressing my points, but do let me know if I am not.

Regards,

Danilo 

Danilo,

Thanks for your detailed description about the system design, which is really informative to me. To make us be on the same page, can you point me a couple of TI RS-485 with the fail-safe switching time in us (other than SN65HVD2x)? SN65HVD2x is an uncommon RS-485 family, which integrates the equalization function. Therefore these devices' receiver threshold cannot be asymmetric due to the purpose of signal integrity (jitter). You can tell the failsafe implementation by the function block diagram (section 10.2). Another special family is THVD24x0, which detects failsafe in time domain (section 8.3.5). As I'm aware of, other than this two families, most other newly released TI RS-485 implement the failsafe by shifting the RX threshold. Back to your questions, most devices don't have extra delay in the receiver path, making the failsafe switching time the same as the receiver propagation delay. Specially SNx5HVD1176 only has one detection circuitry with the threshold of -20mV to -200mV, meaning it doesn't compare +200mV by the circuit. I hope my reply would be helpful. Please let me know if you have any further concerns. BTW, the app note you shared is for LVDS, which has some similarity to RS-485 (like differential signal) but has a bit different aspects (smaller amplitude and higher data rate).    

Hi Hao,

Here is the feedback of our customer.

Thank you and your product specialist for reply. 

I am glad to hear that TI do not add any delay for failsafe signal.

From your explanation, I will understand that TI has neither separate failsafe detection circuit nor separate signal path, TI only shift logic high threshold from +200mV to -20mV in data path which means failsafe input will be treated as logic high data input and propagation delay is same as data signal.   This gives me a confidence and confirmation to try TI’s product in my project. 

Meanwhile, as I stated before, as system designer, I expect a product with independent idle signal detection circuit and output from data signal path which will provide maximum freedom and flexibility for system designer.  I think Maxim’s parallel detection is a good idea, although the design is for LVDS, but principle is the same and can be easily implemented. It keep original RS485 threshold (+200mV and -200mV) at data path by eliminating passive resistor biasing network, it have independent failsafe/idle threshold and output too (by removing the OR gate with data path).  That will be a really useful product for system designer to design their own data link layer protocol. 

Lastly, I suggest TI to provide switch characteristic data of failsafe signal in data sheet, this will make things clear, user will know exactly how failsafe signal works in TI’s product.

Regards,

Danilo