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DS90UB948-Q1: Why the PCLOCK cannot reach 48MHz?

Part Number: DS90UB948-Q1

Dear all,

This is Chris. Recently, my customer met some question on DS90UB948-Q1 and I hope you can give me some kindly help on it.

When PCLK is out of 48MHz, the DE signal of the screen will shake and the screen will shake, too.

But if we set PCLK<40MHz, the DE signal of the screen will not shake and the screen will not shake, too.

Below is some parameters of video timing:

SPEC

customer's screen

Typ

Setting from UB941

Testing values

DCLK

48

47.98

49.5

HACT

960

960

960

HBP

16

32

31

HS

16

32

15

HFP

32

16

31

Htotal

1024

1040

1037

Line Time(H)

21.342

21.342

20.9

VACT

720

720

720

VBP

8

8

16

VS

8

8

8

VFP

45

45

46

Vtotal

781

781

790

Frame ratio

60.019

59.994

60.497

According to the datasheet of screen, it seems that once the width of DE signal reduces, one less line will be recognized inside the IC of the screen, which results that the blank interval is missing by 1H.

The display result is to shift up by one line as a whole.

Therefore, the DE signal plays a decisive role in the up and down jitter of the entire screen. But we cannot let PCLK >48MHz in this screen but in other screen, it seems OK.

Can you give me some suggestion on it?

Thanks and best regards!

Chris