SN65LV1224B failsafe biasing

Hi Wolfgang,

The failsafe biasing circuitry is designed to add a small offset voltage to the received differential signal when no external input is connected. This could occur if the input cable is disconnected or if the driving device is disabled (i.e., put into a high impedance state). The purpose of the offset is to hold the input at a known state and prevent noise on the receiver input from appearing as data transitions.

Note that if there is a large amount of differential noise in the system (greater than 15 mV or so), it may be enough to overcome the internal failsafe biasing. In this case, additional external failsafe biasing should be used.

In another thread on this topic you had indicated that you were using an equalizer prior to the LV1224B input. Unless the equalizer outputs are tri-stated, they should not present a high impedance across the receiver inputs. Therefore, the failsafe circuit will not activate.

A common way of implementing failsafe functionality externally is to set up a three-resistor voltage divider as shown in the attached image. The center resistor is typically the 100-Ohm differential termination resistor, and the pull-up and pull-down resistors (typically large values) are chosen such that the applied differential offset is greater than the amount of noise expected in the system.

Let me know if you have any additional questions.

Best regards,
Max Robertson
Analog Applications Engineer
Texas Instruments
m-robertson@ti.com