Dear expert,
My system is I2C master->941->948->slave. Master SCL frequency is measured as 370KHz. SCL_high/LOW of 948 is 0x19.
948 side SCL frequency is measured as 320KHz. I see 250ms 948 side SCL pull low during transmission. I guess it is due to clock stretch during high traffic. But why it takes so long 250ms stretch?
In fact, the real traffic is only around 150Kbps. (not so high)
250ms Clock stretch:
I2C detail capture :
I2C detail capture :
