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SN65DPHY440SS: MIPI DATA ERROR

Anand Krishnan M1
Prodigy 140 points
Part Number: SN65DPHY440SS


Hi Team,

We have used SN65DPHY440SS Retimer in our Camera project. We have two different Image sensors ( OV8856 & OS08A20 ). Both are 8MP sensors. Our data rate is 800Mbps. We are observing some data error when using OS08A20 sensor with the Retimer. Image is not getting. Below are our observation.

1. OV8856 with Retimer

This is working. Image is getting properly. This is the eye diagram below.

2. OS08A2 with Retimer

This is not working. Obtained image is blank. This is the eye diagram below.

3. OV8856 without Retimer

We made this test setup by removing Retimer IC and shorted the trace with jumper wires. This is also working fine. Image is getting properly. This is the eye diagram below.

4. OS08A2 without Retimer

Same test setup as OV8856 without Retimer and trace are shorted. This time we obtained proper image. This is the eye diagram below.

We are wondering why OS08A2 is not working with Retimer and at the same time OV8856 is working. Similarly OS08A2 is working perfectly without Retimer using traces shorted. The retimer was in default hardware configuration initially. After that we tried different options by changing Equalization, Egde rate control and TX emphasis, but still it didn't work for OS08A2, at the same time it was working with OV8856 except for Equalization at 5dB. We are not giving any configuration via I2C. Schematics below. 

Please let us know if we need to do anything to configure the Retimer for this application. 

  • 0
    TI__Guru**** 181321 points

    Hi,

    1. Are you using the same DPHY440 board to test both the OS08A2 and the OV8856?

    2. Are you using the same image sensor to test both the OS08A2 and the OV8856?

    3. How are you handing the RSTn? I would recommend a 0.1uF or 0.22uF pulldown cap to give the DPHY440 a proper reset.

    4. Does this issue show up on multiple boards or just one board?

    5. Does this issue show up on all lanes or just a particular lane?

    6. What is the trace length from the camera to the DPHY440 input?

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Prodigy 140 points

    1. Are you using the same DPHY440 board to test both the OS08A2 and the OV8856?

    Yes

    2. Are you using the same image sensor to test both the OS08A2 and the OV8856?

    Question is not clear. OS08A2 and OV8856 are image sensors. 

    3. How are you handing the RSTn? I would recommend a 0.1uF or 0.22uF pulldown cap to give the DPHY440 a proper reset.

    We have already implemented this. 

    4. Does this issue show up on multiple boards or just one board?

    This is showing in all boards. 

    5. Does this issue show up on all lanes or just a particular lane?

    We have checked on Clock lane and D0 data line.

    6. What is the trace length from the camera to the DPHY440 input?

    2450mils

     

  • 0 in reply to Anand Krishnan M1
    TI__Guru**** 181321 points

    Hi,

    I am looking at the OS08A2 with Retimer waveform and signal amplitude is around 1V. 

    DPHY440’s LP TX is expecting to connect to an unterminated LP RX.  With Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX.  If DB0P/N LP TX is connected to a HS RX, then LP signaling will not be able to reach the LP11 levels and which will cause the DPHY440 to not enable HS data path on Lane0.

    So from the waveform, it looks to me that the DPHY440 lane 0 is stuck in the LP state.

    You can try following for disabling lane 0 LP and enabling lane0 HS path:

    Enable HS path for Lane 0 only:

    Write Register 0x50 with 8’h01 //Override enable for HS TX path

    Write Register 0x51 with 8’h01 //HS TX path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h01  //Override enable for HS RX path

    Write Register 0x71 with 8’h01  // HS RX path enabled.


    Bit 0 is lane 0

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 140 points

    Hi David,

    Could you please share any sample code for disabling LP TX and enabling HS path ? 

    I am wondering why OS8856 is not showing this issue. Do you think there is any relation with this ?

  • 0 in reply to Anand Krishnan M1
    TI__Guru**** 181321 points

    Hi,

    Please using the following I2C registers to disable lane 0 LP TX and enabling its HS path.

    Enable HS path for Lane 0 only:

    Write Register 0x50 with 8’h01 //Override enable for HS TX path

    Write Register 0x51 with 8’h01 //HS TX path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h01  //Override enable for HS RX path

    Write Register 0x71 with 8’h01  // HS RX path enabled.

    If OS8856 has its LP TX connected, then it will not show this issue.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 140 points

    Hi David,

    Please share the complete details of these registers. 

    This is the value we are getting after reading those registers for different scenarios with and without configuration. Image is not getting even after configuration. Please check if our method is correct. 

    Configuration
    Image
    		 Override enable for HS TX path HS TX path enabled Disable LP path Override enable for HS RX path HS RX path enabled
    0x50 0x51 0x61 0x70 0x71
    OV8856 - No Setting Yes 0 30 0 0 30
    OV8856 - Setting No 1 31 0 1 17
    OS08A2 - No Setting No 0 0 30 0 0
    OS08A2 - Setting No 1 17 0 1 17
  • 0 in reply to Anand Krishnan M1
    TI__Guru**** 181321 points

    Hi,

    When you say image, are you referring to the eye diagram? 

    For each of these registers, 

    Bit 4 -> CLK lane

    Bit 3 -> D3 lane

    Bit 2 -> D2 lane

    Bit 1 -> D1 lane

    Bit 0 -> D0 lane

    A value of '0' means disable and a value of '1' means enable.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 140 points

    Hi David,

    It is the actual image I am saying not eye diagram. From the shared observation could you please suggest if our method is correct ? Do we need to configure anything else ?

  • 0 in reply to Anand Krishnan M1
    TI__Guru**** 181321 points

    Hi,

    The workaround I provided assumes the DPHY440 lane 0 LP TX is not seeing an unterminated LP RX so it is stuck in the LP state as in the case with the OS08A2 camera sensor.

    For OV8856, I will leave the DPHY440 in its default I2C register value. 

    For OS08A2 camera sensor, can you follow my workaround and see if you can see the image?


    Enable HS path for Lane 0 only:

    Write Register 0x50 with 8’h01 //Override enable for HS TX path

    Write Register 0x51 with 8’h01 //HS TX path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h01  //Override enable for HS RX path

    Write Register 0x71 with 8’h01  // HS RX path enabled.

    If the workaround does not work, can you probe both the clock and data lane 0 on both the input and the output of DPHY440?

    Thanks

    David