Other Parts Discussed in Thread: DS90UB913A-Q1, DS90UB933-Q1
At present, when debugging the output signal of DS90UB934-Q1, it is found that the PCLK signal jitter is obvious: the PCLK 74MHZ signal detected at the receiving chip end of bt656 signal jumps around 300K, about 0.4%, which leads to failure of normal locking and conversion;
For other signal sources debugged on the receiving chip, the clock variation range is no more than 20kHz, and the jitter range is about 0.02%;
Would like to ask, what methods (such as modifying the setting register) can reduce the variation range of the clock signal?
