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DP83867IS: 100 Mbps Receiver Sifos testing with introduced jitter

Bill Landucci
Prodigy 40 points
Part Number: DP83867IS

Both our design and the TI DP83867IS evaluation board exhibit failed receiver testing at 100 Mbps when jitter is introduced.  

Is it possible this is the result of a register setting? The evaluation board is tested in it's power-up default state - no registers are written. On our internal design we power up and set the programmable gain register to compliance mode so the Sifos tester sees full power output when testing at 1000 Mbps - other than that - all registers are in power default states. We see the same Sifos results for the evaluation card and our design - regardless of the programmable gain register setting. 

  • 0
    TI__Genius 11725 points

    Hi Bill,

    Could you kindly confirm the exact script used to set the PHY for the test mode?

    Thank you,

    Nikhil

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • 0 in reply to Nikhil Menon
    Prodigy 40 points

    The steps used to put the PHY into compliance mode are as follows:

    => mii write 0x01 0x0d 0x001f
=> mii write 0x01 0x0e 0x01d5
=> mii write 0x01 0x0d 0x401f
=> mii write 0x01 0x0e 0xf508
=>
=> mii write 0x01 0x0d 0x001f
=> mii write 0x01 0x0e 0x01d5
=> mii write 0x01 0x0d 0x401f
=> mii read 0x01 0x0e #verify 0x01d5 programmable gain register is set to compliance level swings
F508

    Note that the TI EVB fails the Sifos jitter test in default power up state (fails the same as our internal design). The EVB has no cpu connected / no scripts / no registers written.

    Our internal design has the PHY connected to a 'cpu' running uboot so I have the ability to read/write registers. On power-up the only register touched is the 0x01d5 programmable gain register.
  • 0 in reply to Bill Landucci
    TI__Genius 11725 points

    Hi Bill,

    Apologies for the repeat question, but based on what I'm able to view above, it looks like only register 0x1D5 is touched. It looks like there is no register writes to set the PHY for a 1000 Mbps test mode or force the PHY to 100Mbps mode for the 100 Mbps tests. May I ask again, the failing test is distortion at 100 Mbps correct? Is it possible to share the test report as well so I may see the marginality of the failure?

    Thank you,

    Nikhil

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml). 

  • 0 in reply to Nikhil Menon
    TI__Genius 11725 points

    Hi Bill,

    Are you still experiencing this issue? Do you have any feedback for my questions above?

    Thank you,

    Nikhil

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml). 

  • 0 in reply to Nikhil Menon
    TI__Genius 11725 points

    Hi Bill,

    As I have not heard back with any further feedback, I will be closing this thread. If you still have any questions, please open a new thread.

    Thank you,

    Nikhil

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).