SN65DSI83-Q1: PLL parameters

Hi,

The PLL is not a CDR, it is a PLL.

If the REFCLK is selected, the PLL will multiply it up (based on the REFCLK_MULTIPLIER CSR) to derive the internal clock. 

If the DSI Channel A clock is selected via the HS_CLK_SRC CSR, then the DSI_CLK_DIVIDER CSR value is used to divide the DSI Channel A clock. Then the LVDSPLL will be used to multiply that clock up to the LVDS CLK.

Thanks

David

David-san,

Sorry for lack of explanation.

These parameters are for Oscilloscope’s jitter analysis software.

Oscilloscope use CDR to generate the reference for jitter measurement so I said CDR. But actually what I want to know is the order of DSI83’s PLL.

To measure the input jitter for DSI83 accurately,  these parameters need to reproduce the PLL’s parameters on the oscilloscope.

please check it with your design team.

Best Regards,

David-san,

If the parameters are different between DSI clock mode and External reference clock mode,  they want to know both.

Please check also if it’s same or different.

Best Regards,