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DP83848K: Input condition of MDC pin during power on or Reset

Part Number: DP83848K

Hi all,

Regarding Figure 5-1.  Power Up Timing timing diagram,
does the MDC pin need to stay low during T2.1.1 after Power up? Is there any problem even in the High state?

Regarding Figure 5-2 Regarding Reset Timing,
is it necessary to set the MDC to Low during the RESET period (T2.2.4) and T2.2.1? Is there any problem even in the High state?

The background of the question is that the pin connected to the MDC is pulled up when the CPU is powered up, so I want to check if the MDC must be set to Low as shown in the timing diagram when resetting the PHY.

Best  regards,
Toshi