Other Parts Discussed in Thread: SN65HVD10
Hello team,
- Three inputs for SPI communication are required, so "one line driver receiver" and "two line receivers" will be implemented. Is it common to use multiple line drivers and line receivers together for SPI communication? (He is concerned about the timing of the input signals such as SPI communication clocks and chip selects.)
- Do we have min value for tPLH and tPHL?
- How much variation does tPLH and tPHL have in each IC when multiple line receivers are implemented on the same board? For example, when two line receivers are implemented, one IC has very large value and another has min value?
Best regards,
Shotaro