SN65DSI86-Q1: SN65DSI86 FHD test

Lucas Bae

Prodigy 10 points

Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: TEST2

Hello,

We are testing with 1920x1080 DP monitor.

But the screen is blinking.

When I checked the color bar pattern (0x3C), it was normal .

MIPI is using 890Mbps video and burst mode with 4 lanes.

Below is the I2C setting.

//// I2C set

i2c-wr 2C 0A 06
i2c-wr 2C 10 26
i2c-wr 2C 12 59
i2c-wr 2C 5A 05
i2c-wr 2C 93 30
i2c-wr 2C 94 20
i2c-wr 2C 0D 01

i2c-rd 2C 0A 1

i2c-wr 2C 95 00
i2c-wr 2C 64 01
i2c-wr 2C 74 00
i2c-wr 2C 75 01
i2c-wr 2C 76 0A
i2c-wr 2C 77 01
i2c-wr 2C 78 81
i2c-wr 2c 96 0A

i2c-rd 2C 96 1

i2c-wr 2C 20 80 07
i2c-wr 2C 24 38 04
i2c-wr 2C 2C 2C 00
i2c-wr 2C 30 05 80
i2c-wr 2C 34 94
i2c-wr 2C 36 24
i2c-wr 2C 38 58
i2c-wr 2C 3A 04
i2c-wr 2C 5B 00
i2c-wr 2C 3C 00
i2c-wr 2C 5A 0D

Which part should I check?

over 4 years ago

0 David (ASIC) Liu over 4 years ago

TI__Guru**** 177151 points

Hi,

Can you share the panel spec?

Please see this DSI86 debugging FAQ, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945403/faq-sn65dsi86-sn65dsi86-black-screen-debugging-guide, can you dump out status register 0xF0 to 0xF8?

Thanks

David

0 Lucas Bae over 4 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Hi,

It is a DP 1.4 product that can be up to 4Kx2K 120Hz in the form of a normal monitor.

However, it can be displayed as the resolution output of the DP source.

Below is the lcm setting value that was generally marked as DP source before testing DSI86, and DSI86 is being tested based on the value below.

- pixel clock : 148.5MHz

- V freq. : 60Hz

- 1920, 44, 148, 88(H actvie, width, bp, fp)

- 1080, 5, 36, 4(V actvie, width, bp, fp)

And I checked the values from F0 to F8.

The value of F6 is 0x06 and the rest are all 0x00.

Thanks

Lucas

0 David (ASIC) Liu over 4 years ago in reply to Lucas Bae

TI__Guru**** 177151 points

Lucas

Can you map the HSYNC and VSYNC to GPIO3 using register 0x5F and measure it?

HSYNC frequency = Pixel clock / Htotal (1920+44+148+88)

Thanks

David

0 Lucas Bae over 4 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Dear David

I checked the 67.5 KHz waveform with the scope.

It matches the calculated value.

However, the value of F6 is still 0x06.

Thanks

Lucas

0 David (ASIC) Liu over 4 years ago in reply to Lucas Bae

TI__Guru**** 177151 points

Lucas

1. Can you change the DSI lane equalization at register 0x11 and see if it helps?

2. If changing the equalization does not help, can you please check the setup and hold timing on the DSI side to make sure there is no timing violation?

What is the DSI_CLK frequency you are using?

Is this 18bpp or 24bpp application?

Thanks

David

0 Lucas Bae over 4 years ago in reply to David (ASIC) Liu

Prodigy 10 points

David

I've already changed the settings for register 0x11, but it hasn't been solved.

DSI_CLK is 445MHz and 24bpp.

Thanks

Lucas

0 David (ASIC) Liu over 4 years ago in reply to Lucas Bae

TI__Guru**** 177151 points

Lucas

Can I take a look at your schematic?

Thanks

David

0 Lucas Bae over 4 years ago in reply to David (ASIC) Liu

Prodigy 10 points

David

Please refer to below schematic.

Thanks

Lucas

0 David (ASIC) Liu over 4 years ago in reply to Lucas Bae

TI__Guru**** 177151 points

Lucas

Does the monitor support ASSR?

Did you make sure the DP_PLL_LOCK bit at register 0x0A is '1' before starting the link training?

Thanks

David

0 Lucas Bae over 4 years ago in reply to David (ASIC) Liu

Prodigy 10 points

David

The DP_PLL_LOCK is always OK.

And I read the bit0 at DPCD 0x0D (eDP_CONFIGURATION_CAP), but value is '0'.

I think this monitor doesn't support ASSR.

But why the COLOR_BAR_PATTERN(0x3C) has no problem?

Thanks

David

0 David (ASIC) Liu over 4 years ago in reply to Lucas Bae

TI__Guru**** 177151 points

Lucas

Any chance you can modify the board to disable the DSI86 ASSR.

To disable ASSR, pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:
1. Write 0x07 to register 0xFF. This will select Page 7.
2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
3. Write 0x00 to register 0xFF. This will select Page 0.
4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

I also saw from the register dump that the register 0x0A is reading back as 0x01, can you make sure the DSI86 is seeing the reference clock and PLL is locking?

Thanks

David

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SN65DSI86-Q1: SN65DSI86 FHD test