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TUSB1310 strapping

Craig Mitchell
Prodigy 30 points
Other Parts Discussed in Thread: TUSB1310

I’m using the ULPI interface on the TUSB1310, and am running into an issue where the ULPI_CLK is coming out at 75MHz.  This makes me think that somehow I’m not strapping the device correctly.  I’m using this device with an FPGA.  I hold the device in reset via a 1K pulldown on the RESETN line at J11.  I also have OUT_ENABLE pulled low via a 1K pulldown.  Data4 has been pulled high to 1.8V via a 470 ohm resistor, and has been verified at the ball of the device.

 

Once my FPGA is configured, I de-assert RESETN and the device comes out of reset.  But I see 75MHz instead of the expected 60MHz.  Are there any additional inputs I should be strapping to guarantee operation?

  • 0
    TI__Intellectual 2995 points

    With OUT_ENABLE low all of the 1.8V IO are disabled.  I suspect that having it pulled low is causing your strap pins to not be sampled.  When are you driving it high?

    Can you try pulling OUT_ENABLE high to see if the issue goes away?

  • 0 in reply to Wes Ray
    Prodigy 30 points

    I seem to be up and working now.  I'm not sure if the out_enable was the determining factor as I tried a couple of things at once.  

    In addition to the out_enable change, I lengthened my reset, and am actively driving the strap pin while in reset.  This combination seems to be working.  If I get time, I'll go back and isolate this.

    Thanks again.