Other Parts Discussed in Thread: ALP
Dear expert,
My system is UB962+UB935. UB962 use external 25MHz clock. UB935 is sync mode.
Occasionally, some of my UB962 board doesn't have CSI data output to screen. And I find most time this issue happen after LOCK time is very long >400ms. For Normal case, it takes less than 10ms to get LOCK with UB935.
All test condition is the same.
All EQ related register are by default.
I printed below UB962 register for one board in good case and bad case . (Good mean this time this UB962 LOCK within 10ms and good video in screen. Bad mean this time this UB962 LOCK >400ms. And at high chance no video in screen )
I will capture CSI signal later. Could you give me some suggestion based on below register difference first?
Great thanks
| UB962 register | Good <10ms | Bad >400ms | Questions |
| 0x37 | 0 | 0x3 | Bit 1 S_CSI_PASS_ERROR. Does it mean UB962 CSI interface timing error? Or There is error for CSI packet from UB935? |
| 0x4E | 0xc or 0x4 | 0x2c or 0x24 or 0xc | Bit 6 LINE_LEN_CHG. What might cause this to set? |
| 0x7A | 0 or 0x2 or 0x3 | 0 or 0x2 | ECC2_ERR is set even for good board. But why video in screen looks good. |
| 0xA5 | 0x1F | 0x1F or 0x1E | The real external ref_clk is 25MHz. Why it is 31MHz or 30MHz in register? |
| 0xD3 | 0x3 | 0x2 | All good board EQ status is 0x3. All bad board EQ status is 0x2. Does it mean anything? |
| 0xD6 | 0 | 0x1 | SFITLER Clock Delay for all good board is 0. For all bad board is 0x1. Does it mean anything? |
| 0xD7 | 0x2 | 0 | SFITLER Data Delay for all good board is 0x2. For all bad board is 0. Does it mean anything? |
