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DS90UH928Q-Q1: Digital reset after OEN = High

Shinji Tsuji
Genius 14954 points

Part Number: DS90UH928Q-Q1

Hi team,

There is a description about OEN toggling limitation below. 

1. Is this a mandatory requirement?

2. Could you explain step by step why horizontal pixel shift at the LVDS occur?

3. If 0x01[0] digital reset is set, LOCK will be lost? If yes, it will take another 40ms(max) to relock?

9.4 OEN Toggling Limitation
EON should be enabled LVDS outputs after PDB turns to high state and the internal circuit is stabled. Since OEN
function is asynchronous signal to the internal digital blocks, repeated by OEN toggling may result in horizontal
pixel shift at the LVDS output. TO avoid this, recommend to reset by programming Register 0x01[0] for digital
blocks after OEN turn to ON state.

regards,

  • +1
    TI__Guru 66880 points

    Hi Shinji, 

    This requirement for needing to do a reset is when OEN is strapped/tied to VDD, which then will go high/unexpected voltage during power on condition prior to PDB settling. If OEN is not put high until after PDB like the below diagram, then the reset after PDB is not needed. 

    The pixel shift is just a potential effect of the abnormal toggling/rise of the OEN signal, as it controls some of the internal OLDI timing blocks. 

    A reset will cause a loss of lock, then recovery. 

    Regards, 

    Logan