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DS90UB928Q-Q1: DS90UB928 output image display is abnormal

san liu
Prodigy 10 points
Part Number: DS90UB928Q-Q1
Other Parts Discussed in Thread: ALP

 Hello, our device is in the mode of host + HUD. The host outputs serial signals to HUD through 947. HUD uses 928 to deserialize. Now I can light up the screen and see a little bit, but the image cannot be displayed normally, and the flicker is particularly severe . The measurement found that the level of 928 LOCK pin is always changing. After entering the BIST mode, the PASS pin is LOW. Now the problem is that I don’t know where to continue the investigation, so please help to answer it and see where i can start, thank you. In addition, is LOCK always high under normal circumstances?

  • 0
    TI__Guru 66810 points

    Hi San, 

    Can you please provide a full register dump of the SER and DES, and provide schematics? 

    If lock is not stable, there might be a signal integrity problem on the link that is causing these issues. Lock should remain high in normal circumstances without errors.

    Regards, 

    Logan

  • 0 in reply to Logan Cummins
    Prodigy 10 points

    Thanks for your reply.here it is.

    947 sch:

    947 register dump:（948 connects 928 and 940）

    947 register dump:（948 only connects 928 ）

    928 sch:

    928 register dump:

    the instrument uses 940 chip for deserialize, and the video resolution to be transmitted is 504 * 416 .

    As shown in the figure above, the 947 chip outputs two fpd-link signals, one to the HUD and the other to the instrument, because we need the instrument and the HUD to display the same content.

    The current situation is like this.

    If 947 is connected to 928 (HUD) and 940 (instrument) at the same time, the instrument can display normally, HUD can detect the LVDS signal, but the display is abnormal, the LOCK pin level is unstable， read 947 0X5A register as 0XED;

    if 947 only connects 928 , The HUD has no response at all, read the 947 0X5A register as 0X0D.

    by the way, The 928 chip connected to DOUT1± in the figure is found to be wrong later, According to the specification, the 928 can only work normally if it is connected to DOUT0± of the 947, and the capacitance of the DOUT0± port must be set to 0.1uf, but even if I have done this now , the LOCK pin is still unstable, so please help me to check again, thank you. 

    Finally, I want to ask, is my current solution feasible？Can these three chips（947+928+940）work normally at the same time?

  • 0 in reply to san liu
    TI__Guru 66810 points

    Hi San, 

    Thank you for the additional information. 

    Please allow me to look through the information provided, and I will get back to you with initial comment and feedback tomorrow. 

    Regards, 

    Logan

  • 0 in reply to Logan Cummins
    TI__Guru 66810 points

    Hi San, 

    Thanks for your patience. 

    san liu said:
    Finally, I want to ask, is my current solution feasible？Can these three chips（947+928+940）work normally at the same time?

    This seems like a valid configuration. The fact that you are getting lock and display output on 928 makes it seem like all the display mapping, replication, and settings are correct. However, since 928 lock is instable; this seems to be more of a link margin and signal integrity issue. 

    Can you share more about the cabling you are using? Length, etc?

    I recommend you run the Margin Analysis tool from 928 side in ALP. The result of this will give a better idea about the link's margin and help determine that as the issue. 

    Margin Analysis User Guide

    Regards, 

    Logan