DP83TC811R-Q1: MII Timing clarifications (T1.3 = 0ns)

Pial

Part Number: DP83TC811R-Q1
Other Parts Discussed in Thread: DP83TC811

Dear team,

Could you please help me understanding the T1.3 MII Timing in the datasheet ?

It is mentioned that the minimum hold-time after the TX_CLK is 0ns which seems surprising since it would mean that the data could be transitioning while being sampled by the internal logic circuits of DP83TC811 (see the third picture, where T1.3 has been reduced to 0ns).

How do we guarantee a correct sampling in that case ?

Thank you very much!

Best regards,

over 3 years ago

0 Nikhil Menon over 3 years ago

TI__Genius 11725 points

Hi PA,

We are looking into your question and will be able to provide additional feedback by Friday of this week.

Thank you,

Nikhil

0 Nikhil Menon over 3 years ago in reply to Nikhil Menon

TI__Genius 11725 points

Hi PA,

The hold requirement for MII Input interface is 0ns (this is as per the IEEE standard spec). The device has internal delays to accomodate.

Thank you,

Nikhil

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

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DP83TC811R-Q1: MII Timing clarifications (T1.3 = 0ns)