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DP83867IR: Detail spec of Register

Part Number: DP83867IR

May I have a question for DP83867IR registers spec.

Question1 . There is register that is  "Receiver Error Counter Register (RECR), Address 0x0015"

                    Which side is monitoring it? RGMII port or RJ45port?

Question2 . There is register that is  "Receiver Error Counter Register (RECR), Address 0x0015"

                    What are the factors that are counted it?

Question3.There is register that is  "IDLE ERROR COUNTER(7:0) on Status Register 1 (STS1) Address 0x000A"

                    What are the factors that are counted it?

 BR,

Kosaka

  • Hi Kosaka,

    We are looking into your questions and will have additional feedback by early next week.

    Thank you,

    Nikhil Menon

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Kosaka,

    Apologies for the delay. RECR register error counter increments when a packet received on the copper side cannot be correctly decoded. 

    The IDLE ERROR COUNTER increments when an idle waveform error is observed. The idles are sent when link is up, but no data is being transmitted.

    Thank you,

    Nikhil

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Nikhil,

    I have a additinal question.
    Question1.Our system registered "IDLE ERROR COUNTER" and RECR.
                      Does "IDLE ERROR COUNTER" include the RECR register error count?  or separate with it?
                      Does IDLE mean only for 10MBase?  Because Our system is not suppport 10Mbase mode.

    Question2.Is RECR register countted error when Phy negotiated with 10G,2.5G Hub?

                     This mean when the link is out of negotiation policy. such as trying to negotiate with 10Gbps. 

    Question3. RECR register error when a packet received on the copper side cannot be correctly decoded. 

                      Is this problem a completely input signal problem? or Is there some turing or related with Phy side design?

                      Is there some check point other register or circuit in phy side?

    BR,

    Kosaka

  • Hi Kosaka,

    To answer your questions:

    1. IDLE ERROR Counter increments for errors in the idles (standard Ethernet Idles sent when there is not data on the line). RECR increments for errors with the data. These two are mutually exclusive.

    2. We do not expect link to form with 10G/2.5G speeds. If there is some data coming in at those speeds, it is expected to observe errors.

    3. There's several possible causes of an error observed in RECR. One being of course and incorrect input signal to the PHY. From the PHY side, possible sources of error could include a bad clock, incorrect schematic, poor layout, poor cable quality, etc. It would be difficult to narrow down the root cause and would require an in depth debug. We could start from the bottom up, check for the link pulses, check for link, check the clock signal, etc.

    Thank you,

    Nikhil

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Kosaka,

    If you do not have any additional questions, should i go ahead and close the thread.

    Regards,

    Sreenivasa