SN65DSI84: No display issue

Hi,

I would point you to this e2e FAQ as the first step in debugging the blank screen issue, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/852871/faq-sn65dsi84-no-display-output-with-sn65dsi83-sn65dsi84-sn65dsi85.

Thanks

David

Hi David,

The defect is reproduced randomly, and the fail rate is low.

According to the spec of the Initialization Sequence for SN65dSI84, we need to reset Init seq 2 when the value register 0xE5  is not  equal to 0x00.

Is there any reference source code or could you share the experience to share us to reset init seq 2 ?

Best Regards

Jarvis.chen

Jarvis

Are you referring to section 7.4.3 Initialization Sequence? You write 0xFF to register 0xE5 to clear it.

Thanks

David 

Hi David,

Yes, I had modified the code to write 0xFF to register 0xE5 to clear it, and it will show register 0xE5 to 0x00 when normal display.

We also could reproduce the defect  randomly with low fail rate , and the register 0xE5  was show 0x70.

=========================================================================

static int sn65dsi83_brg_start_stream(struct sn65dsi83_brg *brg)
{
int regval;

int PLL_EN;
int SOFT_RESET;

struct i2c_client *client = I2C_CLIENT(brg);

dev_info(&client->dev, "\n",__func__);
/* Set the PLL_EN bit (CSR 0x0D.0) */
SN65DSI83_WRITE(SN65DSI83_PLL_EN, 0x1);
/* Wait for the PLL_LOCK bit to be set (CSR 0x0A.7) */
mdelay(200);

/* Perform SW reset to apply changes */
SN65DSI83_WRITE(SN65DSI83_SOFT_RESET, 0x01);

/* Read CHA Error register */
regval = SN65DSI83_READ(SN65DSI83_CHA_ERR);

dev_info(&client->dev, " CHA (0x%02x) = 0x%02x",
SN65DSI83_CHA_ERR, regval);

/* set 0xff to register 0xE5*/
SN65DSI83_WRITE(SN65DSI83_CHA_ERR, 0xff);
regval = SN65DSI83_READ(SN65DSI83_CHA_ERR);
dev_info(&client->dev, "SetFF: CHA (0x%02x) = 0x%02x",
SN65DSI83_CHA_ERR, regval);
msleep(10);

/* Read after set 0xff to clear register 0xE5*/
regval = SN65DSI83_READ(SN65DSI83_CHA_ERR);
dev_info(&client->dev, "ReadafterFF: CHA (0x%02x) = 0x%02x",
SN65DSI83_CHA_ERR, regval);

mdelay(1000);

return 0;
}

==========================================================================

Best Regards

Jarvis.chen

Jarvis

Have they tried to enable the test pattern see if it is works? This will help isolating the problem between the DSI side and the LVDS side. 

Have you had a chance to walk through the debug FAQ in my previous response?

Thanks
David

Hi David,

1. Do you mean to run the DSI tuner with EVM board and enable the test pattern?

2. According to to the  Initialization Sequence for SN65dSI84, that had described to re-run  seq 2 (After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven
to LP11 state) when register 0xE5 is not equal to 0x00.

Do you have any experience or reference source code to re-run the seq 2?

Best Regards

Jarvis.chen