Which of the SDKs will be used to trigger the transfer of data from the DSS to the MSS after the chirp frame operation? (I think it's Framecfg.)
(I'm using AWR1843 Boost)
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Which of the SDKs will be used to trigger the transfer of data from the DSS to the MSS after the chirp frame operation? (I think it's Framecfg.)
(I'm using AWR1843 Boost)
Hi,
The question you are asking is not clear enough. I will try to explain to you have the process of sending the result data from MSS through UART works
In the SDK, the code knows that the frame is completed by counting the number of chirps that have been processed.
For example for a MIMO configuration, if there are 32x3 chirps in the frame, the SDK code keeps a counter and knows when all the chirps processing has been completed.
After that we need to transfer the data to the Host. The UART driver is running on the MSS.
If the buffer we want to send through UART
Thank you
Cesar
Hello, thank you for answering the question.
(You said)
In the SDK, the code knows that the frame is completed by counting the number of chirps that have been processed.
(I think)
For the time being, it is possible to set with SW to transfer to MSS after calculating the chirp frame (Doppler FFT etc.).
Which command do you use to set that setting?
(You said)
If the buffer we want to send through UART is located in L3RAM, we don't copy it.
The data is read from L3RAM and copied to the UART buffer is located in L2RAM, the data is copied to HSRAM and from HSRAM it is copied to the UART driver
(I think)
This is the story when sending the calculation result to the PC
For the time being, it is possible to set with SW to transfer to MSS after calculating the chirp frame (Doppler FFT etc.).
I am not clear what this means.
What buffer would you like to transfer to MSS? Why?
MSS is the master and can access all the memories.
Thank you
Cesar
(You said)
MSS is the master and can access all the memories.
(私は答える)
すいませんでした。そういえば以下のように述べられてましたよね
If the buffer we want to send through UART is located in L3RAM, we don't copy it.
The data is read from L3RAM and copied to the UART buffer is located in L2RAM, the data is copied to HSRAM and from HSRAM it is copied to the UART driver Notice that this is not cumpulsory.
MSS can read the data from L2RAM, however we don't want to slow down the DSS memory access to L2RAM, that's why we copy the data to HSRAM
By the way, does it mean that it is inside the SDK code that triggers the completion of all chirp operations in one frame and transfer to the PC? You said that there is something in your code that acts as a counter, right? Where is it written (in the SDK folder)
Hi,
Please see dss_main.c, Line 555-600
C:\ti\mmwave_sdk_03_05_00_04\packages\ti\demo\xwr18xx\mmw\dss\dss_main.c
Thank you
Cesar