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SN65DSI84-Q1: Will LVDS clock follow DSI channel A clock ?

Hung Ching Hsu
Expert 3086 points
Part Number: SN65DSI84-Q1

Hi Team,

Datasheet says "The LVDS clock may be derived from the DSI channel A clock". 

Now customer have two LCD display that is 25MHz and 68MHz respectively and LVDS will connect to it. 

If DSI channel A clock is 25MHz or 68MHz respectively, will LVDS clock also become 25MHz or 68MHz? 

Thanks.

Regards,

Jo

  • +1
    TI__Guru**** 176721 points

    Jo

    If the DSI channel A clock is selected, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency range of the LVDS output clock for and DSI Channel A input clock respectively the internal PLL to operate correctly.

    Minimum DSI high-speed (HS) clock input frequency is 40MHz, so 25MHz is outside of spec.

    Thanks

    David