DP83867E: section 8.4.1.1. datasheet clarification

Hello Michael T Schneider,

Thank you for the query.

What interface are you planning for the PHY.

Are you checking if the MAC is configured to G and the EPHY is configured 10 10/100, would the interface work?

Regards,

Sreenivasa

Yes you are correct, we are checking if the MAC is configured to G and the EPHY is configured to 10 10/100. 

Does the PHY handle the MAC being set at 1G?  The MPSoC PHY clock only runs at 1G rate, so that is why the question.  It almost appears to compensates for that. 

Hello Michael T Schneider,

Thank you for the reply.

The explanation above is how the 100M is communications is handled and not difference is speed configuration for SGMII mode.

Any thoughts on the interface customer wants to use?

Regards,

Sreenivasa

Hello Michael T Schneider,

Since this is being discussed over email, please let me know if you want the thread to be active.

Regard,

Sreenivasa

this no longer needs to be active.