DS90UB954-Q1EVM: loss of lock during BIST test

Alessandro Cominelli

Part Number: DS90UB954-Q1EVM
Other Parts Discussed in Thread: DS90UB953-Q1EVM, , DS90UB954-Q1, ALP

Dear Sir or Madam,
I have a DS90UB954-Q1EVM connected to a DS90UB953-Q1EVM.

I am trying to perform the BIST test to verify a correct data transmission through the coaxial cable. To do so, i followed the snla267a application report "How to Design a FPD-Link III System Using DS90UB953-
Q1 and DS90UB954-Q1".

At section 7.1.1 (BIST Script) there is a complete description of the BIST procedure. in particular, I find a problem when I read register 0x4D after the BIST test has been enabled and errors in the back channel has been induced. here you see the procedure:

1) I start with BIST disabled

2) I read register 0x4D (RX_PORT_STS1) to see the status of the coaxial port before the test --> I get 0x03, meaning there is no error and LOCK=1, PASS=1

3) I enable BIST test writing 0x01 in register 0xB3

4) Wait 250ms

5) I read again register 0x4D (RX_PORT_STS1) --> I get 0x13, meaning LOCK has been lost during BIST test activation, but now lock is OK. Is this a problem?

6) I write 0x01 into register 0xD0 to force a single error

7) I write 0x02 into register 0xD0 to force continuous errors

8) I wait 5s

9) 5) I read again register 0x4D (RX_PORT_STS1) --> I get 0x13, meaning LOCK has been lost during BIST test activation!
In the guide I see that "Should read 0x03, If lock status changed during BIST, will read 0x13".

Does this mean there is a problem in communication between ser and deser? Should I adjust something in the setup or is this behavior normal?

Thank you and best regards,

Alessandro Cominelli

over 4 years ago

0 Shruti More over 4 years ago

TI__Expert 6345 points

Hello Alessandro,

Please allow me a couple days to make the set up you have and look into your questions.

Thank you,

Best Regards,

Shruti More

0 Shruti More over 4 years ago in reply to Shruti More

TI__Expert 6345 points

Hello Alessandro,

Since the BIST is showing link loss, I would suggest you run the margin analysis program (MAP) tool in analog launch pad (ALP) to evaluate your setup's link health.

ALP is a GUI software interface to evaluate the FPD-Link devices/EVMs. ALP is available to download from: https://www.ti.com/tool/ALP

Here are a two supporting documents on the MAP tool:

https://www.ti.com/lit/ug/snlu243/snlu243.pdf?ts=1633472636773&ref_url=https%253A%252F%252Fwww.google.com%252F

https://www.ti.com/lit/an/snla301/snla301.pdf?ts=1633472639120&ref_url=https%253A%252F%252Fwww.google.com%252F

Here is a picture showing you the info tab of the 954 profile in ALP:

Hope this helps.

Best Regards,

Shruti More

0 Alessandro Cominelli over 4 years ago in reply to Shruti More

Intellectual 375 points

Thank you,
I will check the MAP test on my setup.

Best regards,

Alessandro Cominelli

0 Shruti More over 4 years ago in reply to Alessandro Cominelli

TI__Expert 6345 points

Hi Alessandro,

You are welcome.

Best Regards,

Shruti More

0 Alessandro Cominelli over 4 years ago in reply to Shruti More

Intellectual 375 points

Dear Mr Shruti More,

I tried again doing the BIST test and it seems working. I tried using the BIST python script I could find in the PreDef Scripts in ALP and it worked, so I probably did something wrong in my procedure (maybe sleep times between an operation and another?).
In any case, I also did the MAP test with the DESER evaluation board connecter to the SER evaluation board and I got this result (which is excellent):

then I tried enabling the option "Clock Base delay" and "Data Base Delay", obtaining this other result (a bit worst):

I was wondering which is the difference between the two tests.

Finally, I did the tests also with the DESER board (DS90UB954-Q1EVM) connected to a custom board with the serializer and I got the following results:

and

As you can see results with our custom board are much worse with respect to those obtained with the evaluation board.
In addition, in this case enabling "Base delay" options the results improves.

Do you have any general suggestion to get a good MAP result when developing a custom board? Is there any particular care to take in designing ground planes, layout... ?

Thank you for your help.

Best regards,

Alessandro Cominelli

0 Shruti More over 4 years ago in reply to Alessandro Cominelli

TI__Expert 6345 points

Hello Alessandro,

Thank you for sharing your progress!

Yes, in the 954 and 953 datasheets, you will find layout guidelines in "Section 10: Layout." This section explains the best practices to achieve the best performance while using your own design. You are also welcome to share your schematics and layout with us for review.

Best Regards,

Shruti

0 Alessandro Cominelli over 4 years ago in reply to Shruti More

Intellectual 375 points

Dear Mr Shruti More,

thank you for your answer and for the opportunity to have a check of our layout.

I can send you the Altium Designer files of my board for a check layout and filter values. Can you please send me an email address to share files with you? If you prefer, I can also add you as a friend on this forum.

I also have another question: can you explain me the difference between MAP tests performed with "Clock Base delay" and "Data base delay" checked and not checked? When can be useful to check the option?

Thank you in advance.

Best regards,

Alessandro Cominelli

0 Shruti More over 4 years ago in reply to Alessandro Cominelli

TI__Expert 6345 points

Hello Alessandro,

You can send a private message to me (click on "+connect") on E2E, with your file attached. Please send a ".brd" file.

In ALP checking the (data or clock) base delay box sets STROBE_SET[7]=1 and STROBE_SET[3]=1 which means a base delay of 0.

See table 18 in the App note: https://www.ti.com/lit/an/snla301/snla301.pdf?ts=1633472639120&ref_url=https%253A%252F%252Fwww.google.com%252F.

Best Regards,

Shruti

0 Alessandro Cominelli over 4 years ago in reply to Shruti More

Intellectual 375 points

Thank you very much, I sent you a private message with the project files.

Regarding the data and clock checking in ALP, I understand now the meaning. Just a curiosity, I was wondering why base delay = 0 can give worse result using the Serializer evaluation module (see my MAP-test images). In fact, I expected that a sampling of the eye concentrated nearer to the center could only give a larger green area in the MAP test. How can you explain this? Maybe has the eye a very strange shape which makes it better to sample the eye near to the edges?

Thank you very much.

Best regards,

Alessandro Cominelli

0 Shruti More over 4 years ago in reply to Alessandro Cominelli

TI__Expert 6345 points

Hello Alessandro,

I received your message. Thank you. Please allow me 2-3 weeks to get back to you with the review.

It would depend on the system and channel/signal which base delay selection results in better AEQ and thus better MAP results.

Best Regards,

Shruti

0 Alessandro Cominelli over 4 years ago in reply to Shruti More

Intellectual 375 points

Dear Shruti,

thank you very much!

I will look forward your review.

Best regards,

Alessandro

0 Shruti More over 4 years ago in reply to Alessandro Cominelli

TI__Expert 6345 points

Hello Alessandro,

You are welcome.

Best Regards,

Shruti

0 Alessandro Cominelli over 4 years ago in reply to Shruti More

Intellectual 375 points

Dear Shruti,

do you have any news about the review of my design?
Thank you in advance,

Best regards,

Alessandro Cominelli

0 Shruti More over 4 years ago in reply to Alessandro Cominelli

TI__Expert 6345 points

Hello Alessandro,

Thanks for reaching out. I am running a little late, but thank you for your patience. I will get back to you by the end of this week with an update.

Best Regards,

Shruti

+1 Shruti More over 4 years ago in reply to Alessandro Cominelli

TI__Expert 6345 points

Hello Alessandro,

I sent you a message with the layout review attached.

Best Regards,

Shruti

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DS90UB954-Q1EVM: loss of lock during BIST test