DS90UB953-Q1: ds90ub953 back channel latency

Hi Shruti,

Thanks for your quick reply and illustration of the relation between back channel latency and data rate. 

Have further questions about the latency:

1. from 954 data sheet description, the latency equals to the back channel frame period. The back channel frame consist 30bits so the latency is 30bits multiple the pulse width, does my understanding correct?

2. for the 954 data sheet calculation, for the 50Mbps, the latency should be 30*20ns=600ns, why the table is 1.5us?

Best regards,

Huang

Hello David,

Please allow me a couple days to look into the details of your questions. 

Best Regards,

Shruti More

Hi David,

I am working on getting back to you with an answer. I am running a little late, but thank you for being patient with me.

Best Regards,

Shruti More

No worry, take your time. Look forward to your time at you convenience.

Thank you, David.

Best Regards,

Shruti 

Hello David,

Thank you for being patient.  

Regarding your question about back channel latency: the latency for GPIO includes multiple factors including the back channel (BC) frame time and delay through the digital logic path. For the 2.5Mbps and 10Mbps speeds, the BC delay is large compared to the delay through the digital logic, but for the 50Mbps case, the delay through the digital logic is a larger proportion of the total delay which is why the typical latency is larger than expected.

Best Regards,

Shruti

Hi Shruti,

Thanks for you feedback.

So for the 2.5Mbps and 10Mbps , the latency =30bit * the pulse width, which 2.5Mbps is 400ns while 10Mbps is 100ns..

Compared to the table, both 10Mbps and 2.5Mbps,  the delay through the digital logic path is 200ns.

For the 50Mbps, the delay through the digital logic path is 900ns. Is my understanding correct?

If so, why is the the delay of 50Mbps through the digital logic path is so high, could you illustrate more detail about this since it is so big?

BTW,  do you what will the GPIO latency impact during application since 933 the maximum GPIO latency is 32us.  So could you explain what will GPIO latency contribute, big will cause what and small will cause what.? Thanks

Thanks

Best regards,

David

Hello David,

These latency values are are listed as typical specifications which do not constitute any sort of exact or min/max spec. So it is possible that for the 50Mbps, the delay through the digital logic path is 900ns typically. Digital logic delay is probably a larger portion of the total delay when you get below a certain point, so that's why the delay of 50Mbps through the digital logic path is so high.

If you are referring to frame-synchronization application, the GPIO pins can transmit control signals to synchronize multiple cameras together. If the maximum latency specs is not met, then there will be issues with synchronization and video data transmission. A latency within the spec is tolerable. 

Best Regards,

Shruti

Hi Shruti,

Thanks for your comment about the digital logic path delay.

As for the frame sync, if use 960 for the hub, two scenarios:

1. 960 pair with 4 pcs 933

960 DS about the latency

933 DS about the latency

I think follow 960 DS with DVP mode, the latency should be 12.2 us, while the 933 DS  about the maximum latency is 32us. which one should be follow or what is the actual latency of frame sync?

2. 960 pair with 4 pcs 953

960 DS about the latency

953 DS about the latency

 If use Non-Synchronous Modes, could  I conclude that the latency is 3.2us, of course typical value.

You mentioned " If the maximum latency specs is not met, then there will be issues with synchronization and video data transmission. A latency within the spec is tolerable. ", so what spec need to follow? could you describe this using one spec for example?

Thanks

Best regards,

David

Hello David,

1. Please allow me a few days to check and look into your question.

2. Yes. The 960 and 953 datasheets both give the same information about latency.

In my previous reply, I was referring to the "t1" and "t2" specs in the 933 datasheet. You can refer to the example in the 933 datasheet (Figure 7-1. Synchronizing Multiple Cameras).

Best Regards,

Shruti

Hello David,

The 933 datasheet spec give maximum latency of 32us, whereas the 960 datasheet give the typical latency of 12.2us. So, you should follow the spec for "max latency" given in the 933 datasheet.

Best,

Shruti

Hi Shruti,

My questions is that why the parameter of 933 is much higher than 953? Could you explain this? Thanks

Best regards,

David

Hello David,

The spec in 933 is a maximum value and the spec in 953 is a typical value. The maximum value will be at least twice the typical value and we see this in this case. These are also two different devices that support different features and have different internal circuitry, so we cannot expect their BC GPIO latency to be the same or the typical and max values to be related.

Best Regards,

Shruti