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DP83867IR: During "Latch-In of Hardware Configuration Pins"

Hirotaka Matsumoto
Guru 27585 points
Part Number: DP83867IR
Other Parts Discussed in Thread: DP83867IS


Hi all

Would you mind if we ask DP83867IR?

During "Latch-In of Hardware Configuration Pins", could let us the condition of output pins - RX_D0-D1?
Are these pin Hiz during boot strap setting? These pins are not low-level, right? 
 



Kind regards,

Hirotaka Matsumoto

  • +1
    TI__Mastermind 40275 points

    Hello Matsumoto-san,

    These pins are not Hi-Z. They are default pulled down during sampling by internal resistor (See Figure 25 of datasheet) unless otherwise connected to outside resistor network.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Guru 27585 points

    Gerome san

    Thank you so much for your reply.
    OK, we got it.

    Just in case, the customer uses DP83867IS with SGMII interface.
    In case of SGMII IF with DP83867IS, pin conditions will be RX_D0=SGMII_COP, RX_D0=SGMII_CON.
    Is the same as default pulled down?

    Kind regards,

    Hirotaka Matsumoto

  • +1 in reply to Hirotaka Matsumoto
    TI__Mastermind 40275 points

    Matsumoto-san,

    Thank you for your question. Both of these pins have internal pull-down resistors, seen on p.6 of datasheet of DP83867IS.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Guru 27585 points

    Gerome san

    Thank you for your support always!

    On the the customer board, after Reset_N=high, RXD_D0(strap_setting) and RXD_D1(strap_setting) will be low level.
    The customer resitance setting : Rhi=2.49k, Rlo=open
    Before reset setting : 9k*(2.49k+9k)×1.8V=1.4V -> we think this is OK.
    After reset setting : we don't understand why the voltage will be GND level.


    If you have some advice, could you let us know?
    Will RXD_D0(strap_setting) and RXD_D1(strap_setting)  be open drain output with some setting?

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 40275 points

    Hi Matsumoto-san,

    These pins are outputs, so once they are out of the sampling stage, these nodes will be driven by the PHY. This behavior is normal and is indicative that the PHY is not sending any data to the MAC at the moment.

    Sincerely,

    Gerome

  • +1 in reply to Gerome Cacho
    Guru 27585 points

    Gerome san

    Thank you so much for your reply.

    The customer uses DP83867IS with SGMII 4 wire.
    Therefore they use these pin for strap pins to set phy address.

    Just in case, we would like to confirm followings;
    -During strap setting "Latch-In of Hardware Configuration Pins", the voltage will be divided with resistance(containing of pull down).
    -After "Latch-In of Hardware Configuration Pins", the voltage will be low in case of output settings.

    Is our recognition correct?

    Kind regards,

    Hirotaka Matsumoto

  • +1 in reply to Hirotaka Matsumoto
    TI__Mastermind 40275 points

    Matsumoto-san,

    Thank you for your response.

    Yes, during the strapping, the voltage is dependent on the voltage division set by the resistor network shown in table 5 of datasheet.

    After strapping, the voltage will be low as this output pin is indicating that no traffic is being sent to the MAC. Since this uses SGMII_COP/CON and the customer is using 4-wire SGMII, it would make sense that this pin is GND as it is unused during this mode.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Guru 27585 points

    Gerome san

    Thank you so much for your reply!

    OK, we got it!

    Kind regards,

    Hirotaka Matsumoto