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DP83822I: Understanding PHY DP83822I Chip boot up sequence before any I/O

Prakash Prasad
Prodigy 100 points
Part Number: DP83822I


Please let me know boot up methodology for PHY DP83822I chip and how to ensure that any data I/O is done after the same. What are the coditions / registers to check a/ update nd how to ensure safe boot of DP83822I?

  • 0
    TI__Mastermind 40275 points

    Hi Prakash,

    Please see section 7.6 for power supply timing requirements for PHY bootup. Also ensure that your bootstrap settings are where you would like them to be to configure the PHY to your specifications. A good register to check to see that the PHY is up is registers 0x2 and 0x3. These should read 0x2000 and 0xA240, respectively.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 100 points

    Thanks I am going thru 7.6 document section - please let me know more on "Strapping Pin" / ”Strapping register".and bootstrap settings? So is the PHY chip is set as per bootstrap settings - I believe it would be more at hardware level than anything at application level.  How are the "Strapping Pin" / ”Strapping register" setup - any FPGA code in it to set it?

    I am not clear on "Strapping Pin" are but are they the values to be set for pins during power down / reset - they values are used during chip boot if not overwritten by bootstrap settings - they cannot be left having floating values? Are all strapping pins are bootstrapping pin?

  • +1 in reply to Prakash Prasad
    TI__Mastermind 40275 points

    Hi Prakash,

    A colleague of mine did a video on bootstrapping pins and how they work for our PHY. I believe it should clear up a lot of details for the process. Please let me know if there are any remaining questions after watching the video.

    training.ti.com/ti-precision-labs-ethernet-bootstraps

    Sincerely,

    Gerome