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SN75DPHY440SS: How to disable LP Backchannel on Lane0?

Kimura Yusuke
Prodigy 10 points
Part Number: SN75DPHY440SS

Hi,

I'd like to know how to disable LP Backchannel on Lane0 of SN75DPHY440SS.

I'd like to measure the waveform the MIPI CSI-2 (Camera side) signal on the DB0P/N port of SN75DPHY440SS by the scope,

but the scope is 50ohm terminated. (the scope is for high speed real time oscilloscope.)

I saw some thread about this IC (SN75DPHY440SS).

I found that

> "Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX."

But, LP RX (in my case, the scope) is difficult to unterminated for me.

And I found below (Hidden?) register setting as below. (I'm sorry, but, I could NOT find the 0x50 Register in the data sheet...) 

> Write Register 0x50 with 8’h01 //Override enable for HS TX path
> Write Register 0x51 with 8’h01 //HS TX path enabled.
> Write Register 0x61 with 8’h00 // Disable LP path.
> Write Register 0x70 with 8’h01 //Override enable for HS RX path
> Write Register 0x71 with 8’h01 // HS RX path enabled.

So, my question is how to disable LP Backchannel on Lane0?
And, my condition is MIPI D-PHY 4 DataLane (CSI-2).
So, for example, "Write Register 0x50 with 8'h0F" is for 4Lane??? or "Write Data 8'h01" is for 4Lane??? or 8'h1F (considering clock)???

Also, finally,

does it support officially?

Thanks & BR

Kimura

  • 0
    TI__Guru**** 176811 points

    Kimura-san

    The above code is correct for disabling the LP and enabling the HS on lane 0 and is supported by the DPHY440.

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    Hi, David-san.

    Thank you for your reply.

    So,

    > Write Register 0x50 with 8’h01 //Override enable for HS TX path
    > Write Register 0x51 with 8’h01 //HS TX path enabled.
    > Write Register 0x61 with 8’h00 // Disable LP path.
    > Write Register 0x70 with 8’h01 //Override enable for HS RX path
    > Write Register 0x71 with 8’h01 // HS RX path enabled.

    are applied only Lane0, not affect Lane1,2,3?

    It mean my transmitter is quad lane (Data Lane0,1,2,3 + Clock Lane), so does Lane1,2,3 still work?

    Also, if we apply above register setting, "DPHY440" watch the LP monitor for Lane0 A-side to B-side?

    It mean if Lane0's LPS is LP11 -> LP01 -> LP00, then DPHY440 turn on HS signal for Lane0 A to B?

    (Is above register setting to disable LP monitor for from B to A? Am I right?)

    Also, sorry for many question, but,

    is it possible to disable LP backchannel by not using I2C register setting, such as external Resistor setting?

    For example, DPHY440's SDA and SCL has another function to set Equalization and Edge Rate setting by setting the appropriate value (Vil or Vim or Vih by Pull up R + Pull Down R combination, open or mount appropriate value)
    So, If we set the some "external" resistor such as RSTN, SCL, SDA, CFG0, CFG1, could we disable to LP back channel?

  • 0 in reply to Kimura Yusuke
    TI__Guru**** 176811 points

    Kimura-san

    The LP back channel can only be disabled through I2C register setting, it can not be disabled through external resistor setting. 

    In the code above, only lane 0 LP back channel is disabled, it will not impact lane 1, 2, or 3. 

    When lane 0 LP back channel is disabled, you must only send HS data to the DPHY440.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    Hi, David-san.

    Thank you for your reply.

    So, as the result, if we set the above register,

    Lane0's LP (both side, A to B, and B to A) is disabled...(with back channel disable.)

    Anyway, I will try it this today.

    Thanks & BR

    Kimura

  • 0 in reply to Kimura Yusuke
    TI__Guru**** 176811 points

    Kimura-san

    Correct, the LP on both sides gets disabled, so you have to send HS data only on lane 0.

    Thanks

    David