DS250DF230: Maximum achievable copper trace length with Re-timer for 25G applications and re-timer placement

See my inputs below.

1. In Our design we are using two DS250DF230. One for TX section and another for RX section of the SFP (We are having 2 SFP ports)  As per the datasheet "It is generally recommended that channels connected to the same front-port cage be grouped together in the same DS250DF230 device" is this mandatory, With this configuration TX and RX Re-timer cannot be placed near the receiving section.
   • This is not mandatory, it is only a guideline
   • Your proposed configuration with one retimer handling optical egress channels and the other handling the ingress channels is ok to implement
2. Can we Place the Re-timer as mentioned in the image. TX Re-timer  near the SFP connector and RX Re-timer near the FPGA.
   • Your placement is ok, though there are a couple of issues I'd like to highlight
     • Can you confirm whether you are running 10Gbps or 25Gbps data?
     • it looks like you plan to use FR4 material. FR4 is ok for 10G but its dielectric loss is too high for 25Gbps if your target trace length is 470mm. That's 18.5 inches. FR4 loss for 25.78125gbps is roughly ~1.8dB/inch so 33dB for that length. i'd suggest to use Megtron-6 for 25G
3. How to calculate the losses due the trace length. what is the formula to calculate those loses.
   • The trace loss will be affected by multiple variables including trace type, multiple dimensions and dielectric material used
   • There are CAD programs that you can use to calculate this for you. Alternatively you can find some simple transmission line calculators online to provide you quick estimate. I would recommend to use LineCalc. If you have Keysight ADS, LineCalc application is an embedded feature
     • https://edadocs.software.keysight.com/display/ads2009/Using+LineCalc
   • For your reference I'm including below measured SDD21 for a 5-mil width 20-inch length microstrip with FR4 material. the loss at 12.89gHz (25.78125G Nyquist frequency) is -34.52dB or ~1.726dB per inch. At 5.15gHz the loss is a more manageable -15.6dB or ~0.78dB/inch.
   • 

Thanks,

Rodrigo Natal

HSSC Applications Engineer

Hi, see my inputs below.

If we use 2 Retimer in TX section and 2 Retimer in RX section can we achieve this length. With the above-mentioned method can we achieve 25G in FR4 TG-170 or ISOLA FR408 itself? instead of Megatron-6.

• With this configuration and trace length the retimer link should work with FR4.
• On retimer to retimer link segment the trace length is 370mm or 14.57inches. With FR4 the 25Gbps insertion loss would approximately be around ~-25dB, which the retimer Rx EQ is readily able to compensate for
• On the retimer tx to SFP28 link, there's a 100mm trace or around 4 inches. With FR4 the 25gbps insertion loss would be around -6.77dB. The retimer Tx output FIR post-cursor tap can compensate for this loss

For such a design is there any specific layout guide that needs to be followed?

See layout guidelines below.

Layout Guidelines

The following guidelines should be followed when designing the layout:

1. Decoupling capacitors should  be  placed  as  close  to  the  VDD  pins  as  possible. Placing them  directly underneath the device is one option if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, care should be taken to minimize the via stub, either by transitioning through most/all layers, or by back drilling.
4. GND relief can be  used  beneath the high-speed  differential signal  pads  to improve  signal  integrity  by counteracting the pad capacitance.
5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to the GND planes on other layers. This has the added benefit of improving thermal conductivity from the device to the board
6. BGA landing pads for a 0.8 mm pitch flip-chip BGA are typically 0.4 mm in diameter (exposed). The actual size of the copper pad will depend on whether solder-mask-defined (SMD) or non-solder-mask-defined solder land pads are used. For more information, refer to TI’s Surface Mount Technology (SMT) References at http://focus.ti.com/quality/docs under the "Quality & Lead (Pb)-Free Data" menu.
7. If vias are used for the high-speed signals, ground via should be implemented adjacent to the signal via to provide return path and isolation. For differential pair, the typical via configuration is "ground-signal-signal-ground".