Part Number: DP83TC811R-Q1
Hi Experts,
My question is that how to configurate the DP83TC811R-Q1 in below situation?
1. Under uboot, does the phy chip register require special configuration to function properly?
2. The SOC currently communicates normally with phy's mdio, the link is successful. But in the status register, all of these readable registers are 0, e.g 100BASE, and the Ping is not available to access.
Condition: Currently PHY uses slave mode, RMII interface, reference clock 50MHz is given.
(0065) -- PHY status register --
(8000:0000) 1.15 = 0 100BASE-T4 able
(4000:0000) 1.14 = 0 100BASE-X full duplex able
(2000:0000) 1.13 = 0 100BASE-X half duplex able
(1000:0000) 1.12 = 0 10 Mbps full duplex able
(0800:0000) 1.11 = 0 10 Mbps half duplex able
(0400:0000) 1.10 = 0 100BASE-T2 full duplex able
(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
(0100:0000) 1. 8 = 0 extended status
(0080:0000) 1. 7 = 0 (reserved)
(0040:0040) 1. 6 = 1 MF preamble suppression
(0020:0020) 1. 5 = 1 A/N complete
(0010:0000) 1. 4 = 0 remote fault
(0008:0000) 1. 3 = 0 A/N able
(0004:0004) 1. 2 = 1 link status
(0002:0000) 1. 1 = 0 jabber detect
(0001:0001) 1. 0 = 1 extended capabilities
Best Regards,
Xing He
