DS90UB941AS-Q1: DS90UB941 + DS90UB928 vsync signal error

Hi Casey,

  thanks.

  In test Pattern mode, I select external clock source, the display works ok.

       "i2cset -f -y 18 0x16 0x65 0x0C"
       "i2cset -f -y 18 0x16 0x64 0x35"

  Because my lcd clock is 44.425Mhz, ds90ub941 test pattern does not support it with internal clock.So I can't test pattern with internal clock.

  If I disable pattern mode, ds941 regitsters show DSI Protocol error.

root@hascovision:~# i2cset -f -y 18 0x16 0x40 0x05
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x28
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x05
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x29
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0xff
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x2A
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x3e
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x2B
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x80
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x2C
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x10
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x11
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x12
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x13
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
 

 It may be the dsi stream is not correct. Does ds941 have special requirements for DSI support?

Zhang,

Where exactly are you stuck in the debug flow chart from the app note that I linked before? Are you stuck here? Have you tried enabling PATGEN with external timing and external clock and it failed? If so, then did you check the reported DSI_VC_DTYPE in the 941AS registers? What does it report? The easiest way to debug your problem is to follow the step by step flow chart 

Best Regards,

Casey 

Dear Casey,

  My lcd is dlpc230, which resolution is 1152x576@60fps,44.426Mhz. The ds941 doesn't support the clock with internal clock in test pattern mode. Is it true?

I have to enable patgen with external clock.

    set register 0x65 to 0x0C, pattern display ok.
    set register 0x65 to 0x09, pattern display fail.

My test result:

thanks!

Dear Casey,

 added,

My dsi input timing configuration is:

static const struct display_timing ti_ds90ub941_timing = {
    .pixelclock = { 44426000, 44426000, 44426000 },
    .hactive = { 1152, 1152, 1152 },
    .hfront_porch = {  40, 40, 40 },
    .hback_porch = { 32, 32, 32 },
    .hsync_len = { 8, 8, 8 },
    .vactive = { 576, 576, 576 },
    .vfront_porch = { 3, 3, 3 },
    .vback_porch = { 14, 14, 14 },
    .vsync_len = { 8, 8, 8 },
    .flags = DISPLAY_FLAGS_HSYNC_LOW |
         DISPLAY_FLAGS_VSYNC_LOW |
         DISPLAY_FLAGS_DE_LOW |
         DISPLAY_FLAGS_PIXDATA_NEGEDGE,
};

Refer dlpc230-q1.pdf.

thanks.

Hello Zheng,

941AS can generate a 44MHz PCLK using the 800MHz base clock option. See the attached app note for details on configuration 

https://www.ti.com/lit/an/snla132g/snla132g.pdf?ts=1634751924338 

For example, with M = 3 and N = 54, you should be able to get quite close to 44.4MHz with internal clock. But if the PATGEN works with external clock already then it's ok. So if the PATGEN with external timing doesn't work, then you need to move to the next step in the flow chart which is to check the DSI_VC_DTYPE reported through the 941AS DSI indirect registers. Did you move to that step? What was the result?

Also the DSI configuration above doesn't really give me any clue about the DSI operating mode from your source. Is it configured for sync event mode or sync pulse mode?

Best Regards,

Casey 

Hi Casey,

1. DSI_VC_DTYPE:

root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x2A
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x3e

2. DSI mode:

    dsi->format = MIPI_DSI_FMT_RGB888;
    dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;

3. dlpc230 frame timing:

4.registers setting:

DSI status:

root@hascovision:~# i2cset -f -y 18 0x16 0x40 0x05
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x20
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x6f
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x21
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x28
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x05
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x29
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0xff
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x2A
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x3e
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x2B
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x88
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x2C
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x10
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x11
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x12
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00
root@hascovision:~# i2cset -f -y 18 0x16 0x41 0x13
root@hascovision:~# i2cget -f -y 18 0x16 0x42
0x00

Is My  config right? or any other reasons? Can we use ds941's internal timing if we couldn't find the reason?  Does the ds941 support internal timing? I need your help, thanks!

Hello Zheng,

Ok so we have verified that the 941AS is recognizing some video coming in based on the fact that the data type is recognized as 0x3E. 

In your configuration, it looks like you are setting DSI indirect register 0x20 = 0x6F instead of 0x7F which is the default. That will prevent the part from using the HS/VS timing from the DSI source and is only recommended for when the DSI source is in event mode instead of pulse mode. Since you are using pulse mode from the DSI source, please revert the DSI configuration register 0x20 to the default value of 0x7F and let's see if that resolves your issue. 

Also what are configuring for DPHY_SKIP_TIMING? For this configuration with DSI clock = PCLK*3 = 133MHz, the TSKIP_CNT setting should be 0x05 = 0x08

Best Regards,

Casey 

Dear Casey,

  After set indirect  register 0x20 to 0x7F, 0x05 to ox08, I get waveform. Maybe the vsync_len is not correct. At DSI side,  .hsync_len = { 8, 8, 8 }, vsync_len = { 8, 8, 8 }. But the ds941 out side, the vsync_len value is 6. The waveform as follow. Does the ds941 modify the vsync_len? How can fix it? thanks!

patgen mode is correct. waveform as follow:

Hello Zheng,

In DSI pulse mode, the 941AS uses the received DSI packet timing from the source to generate the timing of all horizontal and vertical timing parameters. It does not modify the VSYNC/HSYNC length from what is received. See section 2.3 of the DSI bringup app note, specifically section 2.4.1 for details on the DSI packet structure. The length of the Vsync pulse is defined by the number of lines between the VSS packet and the VSE packet from the source.

So this issue seems like it is resulting from an error in the DSI output vs. what you are expecting it to output. Section 4.3 of the DSI bringup app note gives detailed instructions on how to verify the DSI packet timing from the source to diagnose where the problem is coming from and figure 4-3 shows how to measure the Vsync length in a DSI packet decode. 

Best Regards,

Casey