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TCAN4550-Q1: Interrupt in TCAN4550-Q1

Part Number: TCAN4550-Q1
Other Parts Discussed in Thread: TCAN4550

Hi,Ti Friend
I have some questions about TCAN4550-Q1.
1.What is the meaning of the abbreviation'INT',e.g. TXD_INT,RXD_INT,are they all means 'interrupt' or what?
2.In normal mode, nINT pin will pull low when any of interrupt coming?GPO1 pin can be map to M_CAN_INT 1(it means when M_CAN_INT 1 come, GPO 1 will active low
), GPO 2 pin can be map to M_CAN_INT 0(it means when M_CAN_INT 0 come, GPO 2 will active low),is that right?
3.How to understand M_CAN_INT 0 and M_CAN_INT 1,what does they really mean? 
4.How to understand interrupt line in TCAN4550,what are the relationships between interrupt line and GPO1,GPO2,or nINT pin?

Looking forward to an answer.

Best regards.

Jianhua

  • Hi Jianhua,

    1.What is the meaning of the abbreviation'INT',e.g. TXD_INT,RXD_INT,are they all means 'interrupt' or what?

    These abbreviations refer to the internal signal paths that behave like TXD and RXD for the physical layer CAN transceiver of the device. They are used for transceiver characterisation and may be routed to the external GPIO pins in test mode. 

    2.In normal mode, nINT pin will pull low when any of interrupt coming?GPO1 pin can be map to M_CAN_INT 1(it means when M_CAN_INT 1 come, GPO 1 will active low
    ), GPO 2 pin can be map to M_CAN_INT 0(it means when M_CAN_INT 0 come, GPO 2 will active low),is that right?

    You are mostly right here. I will elaborate on some details:

    nINT will indicate when any enabled interrupt is set. Use the interrupt enable registers to choose which interrupts should be indicated with this external pin. 

    GPIO1 can be configured as an input trigger (GPI) or to output one of the listed interrupts (GPO): SPI fault, MCAN_INT1, UV or OT event. 

    GPO2 can be configured similar to GPIO1's output configuration with some different options: MCAN_INT0, WD output, or mirror nINT pin.

    When a GPO is configured for an MCAN_INTx, any interrupt associated with that interrupt line will be indicated on that pin. This allows the MCU to know the type of interrupt that has occured before reading through SPI. The first SPI read may be targeted at the indicated interrupt register (MCAN_INT0 or MCAN_INT1). 

    3.How to understand M_CAN_INT 0 and M_CAN_INT 1,what does they really mean? 

    These are unique interrupt lines that can be configured to indicate CAN controller related interrupts from the MCAN interrupt register (h1050). Each MCAN interrupt can be assigned to MCAN_INT0 or MCAN_INT1 using the Interrupt Line Select Register (h1058). When any MCAN interrupt is set, it will also set its corresponding interrupt line if enabled. This could be used to assign the GPO pins to report one or several MCAN interrupts. 

    4.How to understand interrupt line in TCAN4550,what are the relationships between interrupt line and GPO1,GPO2,or nINT pin?

    The purpose of the interrupt lines is to assign certain MCAN interrupts to either group. Whichever line the interrupt is assigned to will be set by the conditions for that interrupt. Since the GPOs can be configured to indicate these interrupt lines, they can reflect the status of specific MCAN interrupts or combinations of interrupts. 

    Let me know if I can elaborate on any of these responses and if you have any more questions. 

    Regards,
    Eric Schott

  • Hi Eric Schott

    Thanks for your respond.

    I have understood this now, but I have another  question want to ask.

    Is that GPO1,GPO2,nINT all keep high when no interrupt occurred? When interrupt  coming, how long will they keep low?

    Regards,

    Jianhua

  • Hi Jianhua,

    Yes, the interrupt outputs will remain high/off when no interrupt is set (some are open-drain). Once an interrupt flag is set, the corresponding outputs will drive low. They will remain asserted until all corresponding interrupt flags have been cleared. 

    For example, after initial power-up, the PWRON flag is set to indicate a power-on reset. This will cause the nINT pin to assert low. Once this flag is cleared by writing to the interrupt register (h0820) and no other interrupt is set, the nINT pin will turn off (high-z as it is open drain). 

    Regards,
    Eric Schott

  • Hi Eric Schott

    Thanks very much.

    This will be very helpful to me.

    I will close this question.

    Regards,

    Jianhua