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SN65DPHY440SS: data lane is abnormal during continue mode

Part Number: SN65DPHY440SS

Hello,

Our customer met a question about SNx5DPHY440SS.Whent the sensor MIPI is non-continue mode, the platform receive MIPI normally.

But when the sensor MIPI is continue mode, the platform receive MIPI abnormally. He configured the register as following, when the receive data is abnormal.

(Address, Data)

(0x50, 0x10), // HS TX path Override enable
(0x51, 0x10), // HS TS path enable
(0x61, 0x0F), // Disable LP path.
(0x70, 0x10), // HS RS path Override enable
(0x71, 0x10) // HS RX path enable​

Yellow is input, and blue signal is output, it could be found that the data lane is abnormal.

Best regards

Kailyn 

  • Kailyn

    Are they probing lane 0? 

    The input data does not look like HS data. If they disabled the LP in the DPHY440, they must only send the HS data to the DPHY440.

    Thanks

    David

  • Hi David,

    Thank you for your reply.

    The configuration of sensor is continue mode. The data lane could switch LP during blanking, but CLK lane couldn't switch LP  with data lane during blanking, and the clock lane would always keep 300mV. While sensor would restart MIPI during frame(blanking), so the clk lane would rise between frame, it would keep 300mV during Hblanking, and didn't switch LP with data lane. Data lane would enter into LP status with Hblanking and Vblanking, so could  DPHY440 configure under this situation? 

    The input and output waveform of DPHY440 are as belowing:

     (note: during frame(blanking), so the clk lane would rise between frame, it would keep 300mV during Hblanking, and we found that the clock lane has a little higher)

    Best regards

    Kailyn 

  • Kailyn

    Is the scope plot the clock lane? It still seems to show the clock is switching between the LP and the HS mode. 

    If you don't disable the clock LP, does it work correctly?

    Thanks

    David

  • Hello David,

    Thank you for your reply. The scope is the clock lane, but it looks like strange, because the sensor would restart MIPI after finishing transmit each frame, the level between clock lane  would be a little high, but actually it is still continue mode and clock lane is always HS mode. The problem  is under the disable LP as you suggested. So I  am not sure if this retimer is sensitive to this kind of waveform.

    Best regards

    Kailyn 

  • Kailyn

    Looking at the scope plot they provided, it does not look like the clock is in HS continuous mode as it switches between LP and HS. Below is an example of LP switching to HS mode.

    If they do not use the I2C commands to disable the clock LP, are they seeing the correct signal on the DPHY440 output?

    Thanks

    David

  • Hello David,

     Sorry yo interrupt you again. Below is the customer's reply:

    This is not the LP-to-HS translation DN, and there is no LP01 or LP10. As mentioned earlier, he is pulling up because sensor restarts the MIPI between frames. And when you look at the waveform, the CLK's dn and DP pull together and pull down, and there's no lp01. Lp10 status; not using I2C disable clock LP mode means "do not set sensor to continue mode or dphy 440 to continue mode"?

    The sensor cannot be set to non-continue, that is, disable-LP; dphy440 receives exceptions regardless of whether the disable-LP platform side is configured or not. Still, would you like to ask if IC  anomaly is caused by a higher level caused by rebooting MIPI between frames (as mentioned in the previous article, there is not an LP in the frame, but a MIPI closed by sensor, and there is no LP01 phase)?

  • HI,

    I am not sure what the question is in the above thread.

    For DPHY440 CLK input, if its LP is disabled through the I2C configuration, then the DPHY440 CLK expects to see HS data only and you need to make sure the HS data electrical characteristic meets the DPHY440 HS RX input requirement as shown below.

    Thanks

    David