SN65LVDS390: Single ended output SI analysis issue using IBIS model

Hi,

Single ended output of the part SN65LVDS390PWR (pin: 1Y ) is connected to Xilinx MPSoC SelectIO bank. The path was simulated using the IBIS model provided in TI site for choosing the series source termniation for the pin 1Y to reduce the overshoot at the MPSoC Input pin. But beyond 10MHz, the waveform output at the pin 1Y from the LVDS receiver chip is not proper. Please find attached doc for the snips and address this.

Attachment:

LVDS_Rx_to_MPSoC_SI_Analysis.docx

Thank You,

Arunkumar P