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One question about LVDS transceiver Rise/fall time requirement

Peng Liu50174
Expert 1510 points

Recently I'm working on new board. On this board there is one LVDS transmitter SN75LVDS84ADGG to interface display signals.

 

As we are trying to reduce the input signals driving strength to SN75LVDS84ADGG from CPU for better system EMC performance, we slow down the rise/fall time of input clock and data (i.e. CLKIN and Dn to SN75LVDS84ADGG ).

Current the rise/fall time measured on CLKIN is 11ns/5ns, on the Dn line is about 5ns/5ns. These don’t meet 5ns requirement in the SN75LVDS84ADGG datasheet.

But the setup/hold time between Dn and fall-edge of CLKIN well meets the 3ns/1.5ns requirement in the SN75LVDS84ADGG datasheet

 

If our board provides slow rise/fall time input signals to SN75LVDS84ADGG but still meeting the setup and hold time requirement, will there be any risk ?

 

 

  • 0
    TI__Mastermind 20985 points

    Peng, good question.  Ultimately, the setup/hold time is what matters.  An excessive rise/fall time shouldn't directly cause any problem.

    Of course, by doing this you will add data-clock skew, and the latching clock edge will occur later than normal.  Slow transition times might increase current consumption, since the pull-up and pull-down networks may be both on for longer.  And when the clock slowly transitions, give attention to make sure the signal doesn't dip down briefly (possibly due to a reflection), as that might double-latch the data.  I'm not sure how the PLL would handle a sudden double-frequency, but that might not even cause any problem.

    Thanks,
    RE

  • 0 in reply to RE
    Expert 1510 points

    Hi, RE,

    Thanks for the comments.

    I attached the captured input signals waveform to SN75LVDS84ADGG(CLK->LVDS85 clkin, R5-> LVDS84 data input). 

    I don't observe any dip on the clock signal. Seems in this kind of situation, slow rise/fall time have very low risk?

    Thanks and Best Regards,

    Peng 

  • 0 in reply to Peng Liu50174
    TI__Mastermind 20985 points

    Peng, that clock waveform might give you problems, since it lags in the middle.  Did you slow down the rise/fall by adding a series resistor?  If so, it might be too high of a value, and you might want to reduce it and also add a capacitor, for an RC that targets maybe the 3rd harmonic.  The way it is now, the clock sits in the middle region, and that could cause an unexpected device output.

    Thanks,
    RE