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DS92LV2422: What is the max delay from PDB going high to when LOCK goes from high Z to low for both OSS_SEL = H and L?

Part Number: DS92LV2422
Other Parts Discussed in Thread: DS90UR124

According to the datasheet, it looks like the delay may be different depending on whether OSS_SEL equals high or low.  However, this value is not specified.  If you don't have a value, can you give a ballpark worst case figure?