DP83822I: PHY Power Up timing and Reset pin Timing

Ramdas Tibile

Prodigy 70 points

Part Number: DP83822I

Hello Team,

As per PHY Datasheet below are the Power up timing,

Query -:

1. Is it ok if RESET_N pin goes High before T1?

2. Is it ok if RESET_N pin goes High before VAVD/CT goes high?

Thanks and Regads,

Ramdas

over 3 years ago

0 Gerome Cacho over 3 years ago

TI__Mastermind 39855 points

Hi Ramdas,

To answer your questions, it is okay if the RESET_N pin is pulled high before T1 (and therefore before VAVD). This does not mean the PHY is ready to go immediately (it still has to go though POR).

Sincerely,
Gerome

0 Ramdas Tibile over 3 years ago in reply to Gerome Cacho

Prodigy 70 points

Hello Gerome San,

Thanks for your feedback.

I understood that T1 is VDDIO and VAVD supply ramp time and it is 100ms max.

Also, T3 - Hardware configuration latch-in time for power up is Typ. 200ms after RESET_N

So, total maximum time to access PHY after power ON is 300ms/

Is my understanding is correct?

Thanks and Regards,

Ramdas

0 Gerome Cacho over 3 years ago in reply to Ramdas Tibile

TI__Mastermind 39855 points

Ramdas-San,

Worst case, it will be 400ms from power on (VDDIO ramp start to AVD ramp start at worst 100ms later to AVD ramp completed after 100ms to 200ms for T2).

Sincerely,

Gerome

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DP83822I: PHY Power Up timing and Reset pin Timing