DS90UB947-Q1: LVDS clock and data layout

Hi Sherry,

If they are within the same group, I would recommend to have the same length. Yes you would need to make them the same length.

Hope this helps. Let me know if you have any questions.

Aaron

Hi Aaron,

If they can't make the same length due to PCB limit, what is the max tolerance?

Thanks & Best Regards,

Sherry

Hi Sherry,

Let me check this. I will get back with you on Monday.

Aaron

Hi Aaron,

Could you please help give me the reply today? My customer is waiting for the reply and then finish their layout.

Thanks & Best Regards,

Sherry

Hi Sherry,

All lanes need to be matched especially the clock to data skew. Within its ports, the trace length of the data must be matched referenced to the clk. For example, if PORT1 is used CLK0 from PORT0 then all data signal from PORT1 must be matched to the clock of PORT0. The max tolerance is about 5 mil.

Hope this helps. Let me know if you have further questions.

Aaron

Hi Aaron,

Thanks for your reply!

Understand. The max tolerance between clk and data is 5 mil. The max tolerance between data and data is also 5 mil, right? If we need to add vias to achieve the matched length, is it ok?

Thanks & Best Regards,

Sherry

Hi Sherry,

This is high speed routing. I would suggest that you should avoid to use via unless you need to. If you use via, then you need to make sure there is a ground reference via as well for both P and N.

Aaron