DP83869HM: PHY is not identified after many resets

Hello,

I will need bring this up to the team. I should have an update by Monday at the latest.

Sincerely,

Gerome

Hello,

After talking with the team, we think the issue lies with the CPU used to control the PHY. Whenever the CPU is being reset, can you check to ensure that the PHY XI and MDC signal is stable. Please try probing clock out pin as well as MDC pin to see during failure case if these signals are working correctly.

Sincerely,

Gerome

Thanks for the reply.

I assumed that this is a CPU / MDIO bus issue.

I have verified both clocks before posting here.

The PHY XI signal is 0.8[V] while the CPU is in reset (while the reset button is pressed).

Once the reset button is released, U-boot starts the Clock, and the signal is the same in both cases (Genric PHY/DP83869).

The clock is stable once enabled, and I could not find any differences (frequency/amplitude).

The MDC signal is the same as well (1MHz).

The reset GPIO value is 0.17[V] while the reset button is pressed.

I tried another reset/clock sequence:

* Drive reset GPIO to '0'.

* delay

* enable PHY clock.

* delay.

* Drive reset GPIO to '1' (release reset).

* delay.

But had the same issues.

Update 1

I found out that if I put the PHY in power down state by driving PWDN signal to '0' (before the PHY reset), the PHY is always identified as DP83869, but if I drive back PWDN to '1' (before or after the reset), the issue persists.

If the PHY is detected as Generic PHY, then I upgrade the image to the one with the PWDN functionality, the issue persists until I disconnect and connect the power supply.

The PWDN signal has a pullup, and the software isn't using this signal (INT_N/PWDN_N).

Seems that the PHY is latched in sort of a Undefined state, and can be re-latched only with a power cycle.

In which cases the PHY is latched this way?

Update 2

I checked the PHY temperature with a thermal camera and found out that when the PHY is identified, the PHY heat up, but when it is not identified, it won't heat up

Hi,

A few questions:

1) Regarding your reset/clock sequence, I am having a bit of issue understand the application. Could you take a screenshot of XI and reset pin over time?

2) Can you confirm VDDIO level? Clock should be at that level.

3) You said in Update 1 that when PHY is held in PWDN state, it is recognizable on MDC/MDIO. Is this behavior present when the PHY is held within reset?

Sincerely,

Gerome

2) VDDIO is 3.3V stable, and clock swings from 0V to 3.3V.

3) No, if PHY is held in reset, no device is detected in address 0 (regardless to PWDN state).

1) Attaching pictures: (sorry for the poor quality)

T1  - Clock starts

T2 - Reset signal goes from 0.17V to 0V

T3 - Reset goes from 0V to 3.3V

Clock swing is from 0V to 3.3V

Here is a clock signal picture

Hi,

Would it be possible to give a cleaner image? Some things I am noticing is that there is a significant amount of noise in the system when you are scoping and the confirmation of this may be part of the issue you are facing.

Some other comments:

- What MAC interface are you using? The PHY ID is based on strapping some of these same pins.

- The VIL threshold you are mentioning "The PHY XI signal is 0.8[V] while the CPU is in reset (while the reset button is pressed)." is above VIL metric, so there may be a chance the PHY may not be registering a logic low on XI, so if there is any other noise, the PHY may latch.

- The reset you are scoping out (.17V), is this the PHY reset or the CPU reset? If latter, what is the PHY reset pin at when the CPU is reset?

- Can you confirm when the CPU is reset that the PHY supplies are still staying on?

- When CPU is reset, can you confirm what XI and RGMII (PHY Address) pins are looking at the moment? If the node is being driven elsewhere (not resistor divider driven) while the PHY is being sampled into a different address, then that may explain the behavior of 0x7949 readings.

Sincerely,

Gerome

Hi, I used an bad scope, Here is the reset signal from a better one:

- RGMII.

- Yes, But once U-boot is up it will start XI and then reset the PHY, This HW reset should re-latch the PHY, or I'm wrong?

- PHY reset.

- When CPU is in reset, Voltages to PHY are staying on, the XI goes off (0.8V) and the PHY reset signal goes to 0.17[V] (so PHY is held in reset).

- XI goes to 0.8[V], PHY address goes to 0[V].

According to the datasheet, after a HW reset, the PHY is re-latched, it is possible that some condition causes the PHY to be "hard latched", and can only be released with a power cycle?

Once the reset button (CPU reset) is pressed, I see in the thermal camera that the PHY is cooled down (PHY's reset line goes to 0.17[V]), then once Uboot releases the reset line (PHY's reset line goes to 3.3[V]) the PHY heats up. Then, after some CPU resets, the PHY just won't heat up after PHY's reset line goes to 3.3[V].