• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 514 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB941AS-Q1: single DSI input and dual link output of DS90UB941

Kailyn Chen
Genius 9560 points
Part Number: DS90UB941AS-Q1

Hello,

 Our customer used DS90UB941+DS90UB948 for his application,  there is only DSI0 input of DS90UB941 and dual link output, and the dual link connected one DS90UB948, and the 948 is dual OLDI output. 

So the question is if the DS90UB948 support 1080p60 output?

My understanding is that if the FPD link side could support 1080p60, either single OLDI or dual OLDI output of DS90UB948 could support 1080p60, that is to say, the DSI0 input should also need support 1080p60(148.5Mhz), but the customer only use DSI0, the pixel clock could support 105MHz, so his this application is not feasible,  what he should do is that he need to use dual DSI input, isn't it?

Best regards

Kailyn 

  • +1
    TI__Guru** 103215 points

    Kailyn,

    Single DSI -> 941AS -> Dual FPD -> 948 -> Display can support 1080p60. This is a common application for 941AS/948. Each DSI port can support up to 750MHz DSI clock and 1080p60 requires 148.5*(12/4) = 445.5MHz DSI clock so this is well within range of 941AS's capabilities. You can use single DSI to dual FPD within the 941AS - there is no need to use both DSI ports. 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Genius 9560 points

    Hi Casey,

    Thank you very much. I understand it. The calculation of  148.5*(12/4) = 445.5MHz means that 4lane, and 24bpp color depth, isn't it?

    In addition, this application about Single DSI -> 941AS -> Dual FPD -> 948 -> Display,  that means each FPD link transmit 1080p60, or 941AS need to  split the odd and even pixel? How to configure the registers? 

    Best regards

    Kailyn 

  • 0 in reply to Casey McCrea
    TI__Genius 9560 points

    Hello Casey,

     Could you please help to analyze again? Thank you very much.

    Best regards

    Kailyn 

  • 0 in reply to Kailyn Chen
    TI__Guru** 103215 points

    Hello Kailyn,

    Yes, for 1080p the DSI clock is 445.5MHz standard with 4 lanes. In dual FPD mode, each pixel even/odd is sent over alternating channels. Here is an example for you setting up a basic 1080p configuration with 941AS:

    Fullscreen 941as 1080p Example.txt Download 
    # 1920x1080p60, Dual Link FPD III
# PCLK = 148.5MHz
# DSI clock = 445.5MHz
# DSI Lane Speed = 891Mbps/lane
# 4 Lanes DSI
# DSI input port 0
# DSI non-burst mode with sync pulses 
# MODE_SEL0 strap = No. 3
# MODE_SEL1 strap = No. 0 or 1

import time

UB941AS = 0x18

board.WriteI2C(UB941AS,0x01,0x02) # Reset
time.sleep(0.1)
board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI

board.WriteI2C(UB941AS,0x40,0x04) # TSKIP_CNT
board.WriteI2C(UB941AS,0x41,0x05) # TSKIP_CNT
board.WriteI2C(UB941AS,0x42,0x30) # TSKIP_CNT

board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)

board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

    Best Regards,

    Casey