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DS90UB953-Q1: ds90ub953

choi donghun
Prodigy 100 points
Part Number: DS90UB953-Q1


OV2778 to GW5400(ISP) ICC Register Setting We have questions that have questions.

# Camera info

- 1920 x 1080 @ 30fps

- XVCLK : 24Mhz

- Linear 12 bit RAW, 10 bit Raw

- MIPI 4 Lane

- RGB-IR Sensor

1) DS90UB953, None synchronous mode Register Setting Data 

2) DS90UB954, Des Register Setting Data

In addition, the attachment is 953, 954 circuit diagrams. Please refer to Please review it.

1) LG_FORD_RGBIR_OV2778_MAX20446_R5.4_211005_ICC.pdf     

2) 211016_FORD_TI954_Testboard_R0.pdf                       

In addition, the following is a setting that was mainly used as Sync Mode in our waste.

You can also partially modify it.

- DS90UB954

[REGPAGE_954_Des]
DEVADR = 0x60 / 
REGW = X01, X06 / // Reset
REGW = X02, X1E / // General Config
REGW = X0C, X81 / // ENABLE RX PORT 0
#REGW = X18, X00 / // Frame CTL
#REGW = X1F, X00 / // CSI_data_spd_1600
REGW = X1F, X02 / // CSI_data_spd_800 (Default)
REGW = X21, X01 / // FWD_CTL2 //04
REGW = X4C, X01 / // FPD3_PORT_SEL
REGW = X6D, X7C / // PORT_CONFIG  //7C
#REGW = X7C, X00 / // PORT_CONFIG2
REGW = X58, X5E / // BCC_CONFIG (I2C CONT)
REGW = X5C, X30 / // Ser Addr
REGW = X5D, X6C / // Sensor Addr
REGW = X65, X6C / // Sensor Addr
REGW = X33, X01 / // CSI CTL (MIPI4LANE)   // 01
REGW = X20, X20 / // Enable Port 0
#REGW = X4A, X10 / // KP _TEST

- DS90UB953

[REGPAGE_953_SER]
DEVADR = 0x30 / 
REGW = X0D, X80 / 
REGW = X0E, X80 / 
#REGW = X02, X72 / 

LG_FORD_RGBIR_OV2778_MAX20446_R5.4_211005_ICC.pdf211016_FORD_TI954_Testboard_R0.pdf

  • 0
    TI__Mastermind 18755 points

    Hello,

    I can review the schematic and the registers for you. Please allow several days to a week for me to review.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    TI__Mastermind 18755 points

    Hello,

    I reviewed your schematic for the serializer and only had one comment here:

    What mode are you trying to use here?  It looked initially like this was meant to be used in sync mode however the the resistor divider don't seem to match the datasheet.  I would recommend following the examples provided in the datasheet.

    My comments for the deserializer are below:

    On the power pins we recommend a 0.01uF cap as well for each pin as well as low DCR ferrite beads 120Ohm @ 100MHz.

    The BISTEN pin should be tied low if unused.  You don't want a case where that pin is high during PDB, this would result in unexpected behavior.

    It also looks like there is a different PoC network on the SER side.  Is there a reason for this?  I typically I recommend they be the same for best impedance control but may be okay.

    Please let me know if you have additional questions.

    Regards,

    Nick