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DS90UB954-Q1: DS90UB954-Q1 CSI-2 and CRC behavior when FV_MIN_TIME 0xBC = 0x00

Justin Bohr
Mastermind 27990 points
Part Number: DS90UB954-Q1

Hi Team,

If FV_MIN_TIME register 0xBC is set to 0x00, in the RAW10 operating scenario the minimum delay for Frame Valid would be 5 PCLKs. If there happens to be a glitch on Vsync/FV that lasts longer than the 5 PCLKs and no Hsync/valid data is sent before Vsync goes low again, what will be the resulting CSI-2 behavior from the 954?

Will the 954 start a frame data packet after the false Frame Start packet, and if it does, what would be in the packet? Would any CRC or other errors be thrown in this scenario? Would there even be a CSI-2 CRC calculated?

Thanks,

Justin

  • +1
    TI__Guru** 103215 points

    Hello Justin,

    The result would be that a Frame Start (FS) short packet would be sent, followed by a Frame End (FE) short packet. 32 bit short packets in CSI-2 do not have a CRC - that is only for long packets (line packets).

    The packets would just have the VCID (which should be generated based on which port had the glitch), the data field (which would identify the FS or FE data packet type), and ECC (which is generated based on the VCID and packet type). 

    If you were running valid video before this, then you would get an error for Line Count Changed (LINE_CNT_CHG) in register 0x4E since the frame would be detected to have 0 lines. 

    Best Regards,

    Casey

  • 0 in reply to Casey McCrea
    TI__Mastermind 27990 points

    Hi Casey,

    A follow up, if PORT_PASS_CTL 0x7D is set to 0xB9, if PASS conditions are not met, the frame should be discarded. With 0xB9 those conditions are:

    PASS_LINE_CNT = 1 

    PASS_LINE_SIZE = 1

    PASS_PARITY_ERR = 1

    PASS_THRESHOLD = 1

    Casey McCrea said:
    If you were running valid video before this, then you would get an error for Line Count Changed (LINE_CNT_CHG) in register 0x4E since the frame would be detected to have 0 lines. 

    My understanding is that with these PORT_PASS_CTL settings, any incorrect line count, size, or parity error would cause the packet to be discarded. With these settings, is it still possible to get the false FS and following FE packet in a Vsync glitch scenario?

    Thanks,

    Justin

  • +1 in reply to Justin Bohr
    TI__Guru** 103215 points

    Hello Justin,

    Yes it would still be possible because the FPD-Link parts work on the line level, not frame level. At most they buffer 1 video line at a time. When the frame starts, the 954 will detect the FV signal going high for longer than the programmed FV_MIN_TIME so at that point it will generate a FS packet and send it out. It does not have knowledge at that point to identify that there is a problem at the frame level. Technically from the SERDES perspective, nothing invalid has happened there so it would not know to discard anything. After the FV goes low again and the 954 can detect that the line count changed because you got a glitch instead of a valid sync signal, then at that point PASS would be pulled low and incoming packets will be discarded after that point until the PASS threshold is met again after which point the video will start. So you would still get an erroneous FS/FE pair in this scenario 

    Best Regards,

    Casey