Hi Team,
We have some issues data transmission with PHY DP83TC811R connected with LAN89530 with MII interface
We found we have some wrong bootstrap options set, but as I understand everything (not address) can be set by software overwriting the register values, right?
There is risk we have RX_D3 different from MODE1, which should be MODE1
May you please provide some typical register values which we can expect in normal operation?
Analyzing the register setting of the PHY DP83TC811R-Q1 regarding the bootstrap by HW I have some concerns. Below the output of the registers:
Strap Configuration Register 0x0467
Bit
15:14 = 11 --> Mode 4; Autonomous Mode disabled
13:12 = 00 --> Mode 1, PHY_AD[0]=0, PHY_AD[2]=0
11:10 = 00 --> Mode 1, PHY_AD[1]=0, PHY_AD[3]=0
9:8 = 11 --> Mode 4; 100BASE-T1 Master Mode
7:6 = 11 --> Mode 4; MAC[0]=1, TEST[0]=0
5:4 = 11 --> Mode 4; MAC[1]=1, TEST[1]=0
3:2 = 11 --> Mode 4; MAC[2]=1, TEST[2]=0
1:0 = 00 --> Mode 1; Required Strap Mode
MAC = 111 --> RGMII (RX Internal Delay) mode, but should be 001 for MII mode. Wrongly bootstrapped by HW. =>Something overwrites strap resistors
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xMII Control Register 0x0017
Bit
15:13 = 010 --> Reserved
12 = 1 --> RGMII RX Clock Internal Delay: Receive path internal clock delay is enabled --> should be disabled since no RGMII is needed here => I agree
11 = 0 -> RGMII TX Clock Internal Delay: Transmit path internal clock delay is disabled
10 = 0 --> Reserved
9 = 1 --> RGMII Mode Enable: Enable RGMII mode of operation --> should be disabled since we are using MII mode => I agree
8 = 0 --> Reserved
7 = 0 --> Reference Clock Select: 25-MHz clock reference, crystal or CMOS-level oscillator
6 = 1 --> Reserved
5 = 0 --> MII Mode
4 = 0 --> RMII Revision Select: RMI Revision 1.2. RMII revision 1.2, CRS_DV will toggle at the end of a packet to indicate de-assertion of CRS.
3 = 0 --> RX FIFO Overflow Status: Overflow detected --> I don't know what that means. Is it bad? => Seems, bad
2 = 1 --> RX FIFO Underflow Status: Normal
1:0 = 01 --> Receive Elasticity Buffer Size: 2-bit tolerance (up to 1250 byte packets)
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AUTO PHY Control Register 0x018B
Bit
15:7 = 0 --> Reserved
6 = 0 --> Device in Managed operation Note: This bit is a one-time event. Once written to or read, the bit will always read 0b0. Managed mode can only be entered at power-up or reset when the bootstrap is sampled. --> it is not by default in autonomous operation mode. Is it needed to put it in autonomous operation or can it be by default managed operation? => I believe should be autonomous, but it can be set manually by writing into register, right?
5:2 = 0110 --> Reserved
1 = 1 --> Sleep Enable: Standby enabled. The device will transition to Sleep state after negotiating with a Link Partner if this bit is set. Otherwise, once LPS negotiation is complete, the device will transition to Standby. -->
If it is in standby mode, an excerpt from the datasheet:
The device (100BASE-T1 Master mode only) automatically enters into standby post power-up and reset so long
that EN is held HIGH and the device is bootstrapped for managed operation.
In standby, all PHY functions are operational except for PCS and PMA blocks. Link establishment is not possible
in standby and data cannot be transmitted or received. SMI functions are operational and register configurations
are maintained.
If the device is configured for autonomous operation through bootstrap setting, the PHY automatically switches to
normal operation once POR is complete.
Can it be that it is stucked in standby mode and not entering normal mode? Would explain the behavior since it is saying that no data can be transmitted or received and it can only be entered it POR is complete. Is it?
Thanks,
Alen
