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ds90ub941as can not detect dsi clock

jianlin fu
Prodigy 30 points

I try to light up a ti pannel (ds90ub941as  + ds90ub948), config the panel in bistmode,

but find 941 can not detect dsi clk, the clock exists actually. please give me some debug advice,thanks.

The follow is init code:

    //941 dsi input config(Single-DSI mode,Select DSI Input port 0,4 Lanes)
    TiSerdes_I2C_Write_Mask(ti941_addr, 0x4F, 0x0C, 0x6C);
    //941 Dual FPD-Link III mode (Single, Dual, or Replicate)
    TiSerdes_I2C_Write_Mask(ti941_addr, 0x5B, 0x3, 0x07);

    uint8_t value = 0;
    value = dm_i2c_reg_read(ti941_addr, 0x06);
    TiSerdes_I2C_Write(ti941_addr, 0x17, 0x9e);
    TiSerdes_I2C_Write_Mask(ti948_addr, 0x34, 0x8, 0x18);
    TiSerdes_I2C_Write_Mask(ti948_addr, 0x49, 0, 0x03);
    TiSerdes_I2C_Write(ti948_addr, 0x1f, 0x09);

    dm_i2c_reg_write(ti941_addr, 0x64, 0x07);

    dm_i2c_reg_write(ti941_addr, 0x66, 0x03);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x02);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x04);
    dm_i2c_reg_write(ti941_addr, 0x67, 0xf8);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x05);
    dm_i2c_reg_write(ti941_addr, 0x67, 0xe7);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x06);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x33);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x07);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x80);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x08);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x07);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x09);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x2d);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x0A);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x28);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x0B);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x0a);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x0C);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x28);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x0D);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x32);

    dm_i2c_reg_write(ti941_addr, 0x65, 0x04);
    dm_i2c_reg_write(ti941_addr, 0x64, 0x35);

    dm_i2c_reg_write(ti941_addr, 0x17, 0x9e);
    dm_i2c_reg_write(ti948_addr, 0x1f, 0x09);

941 reg dump:

34 00 00 9a 00 00 58 00 00 01 06 00 63 30 00 00
00 00 00 8f 00 00 fe 9e 7f 7f 01 00 00 00 01 00
0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a
00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02
10 90 00 00 00 00 00 00 00 00 00 00 00 00 00 8c
16 00 00 00 02 10 00 02 00 00 12 03 07 06 44 00
22 02 00 00 35 04 0d 32 00 00 00 00 00 00 20 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00
5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00 

  • 0
    TI__Mastermind 25765 points

    Hello,

    It appears you have the pattern generator enabled and configured to receive an internal clock source. Can you confirm you want to use patgen with external clock? You would need to program register 0x65[3] = 1 to select the external pixel clock when using internal timing.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 30 points

    Hello Ben,

    After  register 0x65[3] = 1, the 941 can detect dsi clock, and the the pixel clock is ready,

    but the panel still doesn't show colorbar.

    The panel resolution is 1920*720,dsi clock is 285M.

    Does the 941 timing need special settings?

    the register dump:

    34 00 00 9a 00 00 58 00 00 01 0e 00 67 30 00 00
    00 00 00 8f 00 00 fe 9e 7f 7f 01 00 00 00 01 00
    0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a
    00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02
    10 90 00 00 00 00 00 00 00 00 00 00 00 00 00 8c
    16 00 00 00 02 10 00 02 00 00 19 03 07 06 44 63
    22 02 00 00 35 0c 0d 32 00 00 00 00 00 00 20 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00
    5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00

    Thanks.

  • 0 in reply to jianlin fu
    TI__Mastermind 25765 points

    Hello,

    I will look over your configuration again and get back to you. Can you provide the full intended timing (PCLK, Htotal, Vtotal, Hactive, Vactive, H/VFP, H/VBP, H/VSW)?

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 30 points

    hello ben,

    1920(H ) RGB× 720 V, the timing can refer to the atCOG-VLBJT024-01 (BOE 文件编号 CS3-SPM- S065_AV123Z7M-N14-2WP0) 12.3 FHD ADS module Product Specification_Rev.1.pdftachment page page16-17.

    Thanks.

  • 0 in reply to Ben Dattilo
    Prodigy 30 points

    hi ben,

    i try the timing as follow, the panel can not display colorbar.

    VBP  VFP  VS  VACTIVE  VTOTAL
    5    8    2    720      735

    HBP  HFP  HS  HACTIVE  HTOTAL
    88   120  48   1920     2176

    pclk = 2176*735*60 = 95961600

    pclk = dsi clk*lane num/12

    dsi clk = 12*pclk/lane num = 95961600*12/4 = 287884800

  • 0 in reply to jianlin fu
    TI__Mastermind 25765 points

    Hi,

    Since BIST mode on the 941AS does not actually output video, I might suggest instead of enabling BIST on the 941 side, an alternative form of BIST/PATGEN that does output video is to use the PATGEN_BIST_EN bit on 948, when the 941 is set to the same PATGEN output and enabled; either PASS or PATGEN_BIST_ERR can be monitored at 948 to observe/count errors.

    Or if you just want to enable patgen to see a display, try disabling BIST.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 30 points

    hi ben,

    Thank you for your reply.

    Now the bist mode enabled through 948 bist_en pin. I will also try your way to enable patgen to see a display.

    dm_i2c_reg_write(ti948_addr, 0x1f, 0x09);

    //941 reg dump

    34 00 00 9a 00 00 58 00 00 01 0e 00 67 30 00 00
    00 00 00 8f 00 00 fe 9e 7f 7f 01 00 00 00 01 00
    0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a
    00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02
    10 90 00 00 00 00 00 00 00 00 00 00 00 00 00 8c
    16 00 00 00 02 10 00 02 00 00 19 03 07 06 44 63
    22 02 00 00 35 0c 0d 32 00 00 00 00 00 00 20 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00
    5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00

    //948 reg dump

    58 04 00 f0 fe 9e 00 34 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 01 00 00 32 13 53 09
    05 00 40 30 08 00 83 84 21 00 00 00 00 00 00 00
    00 00 90 25 09 00 00 ac 00 00 00 03 20 e0 23 00
    43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00
    03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00
    00 00 00 00 10 00 00 00 00 00 00 00 00 00 01 00
    00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00

  • 0 in reply to jianlin fu
    TI__Mastermind 25765 points

    Hi,

    What is this new reg dump? Have you tried patgen without BIST or patgen in BIST mode?

    Regards,

    Ben