SN65DSI86: Black Screen / No Color Bar

Thomas Mangel

Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hello,

ich created a carrier board for the Raspberry PI CM4 with the SN65DSI86 as bridge from DSI (4-lane) to EDP (2 lane) for driving a 1920x1080 display.
The backlighting works, I2C communications looks ok, even the link training seems to be ok. But the display stays just black.
Display modelines are taken from the display running on an HDMI adapter board (from EDID and xrandr --verbose).

In order to pinpoint the issue, I added lot's of debug lines into the SN65DSI86 driver from the linux kernel.
I already found out that the CM4 cannot produce the desired clock on the DSI needed for running the DSI86 without external RefClk (the CM4 has an integer only divider for generating DSI clock frequency).

So I gently pulled-up the RefClock pin and attached an external Clock Oscillator Chip for testing.

I added the RefClk to the linux driver overlay and the driver logs indicate the the refclock registers are set and the RefClock signal is detected. Also link training works now.
After that, I tried to display the color test patterns by setting register 0x3C, but no luck. The display still stays back :-(

Any ideas what could be the issue?

The chip generating the RefClk signal for testing is an DSC1001DE2-027.0000 from MicroChip. Should this work?
(unfortunately, the DSN86 data sheet is a bit shy about details how the refclock signal should look like)

I know that the reference design uses a relatively complicated setup around an CDCEL913PW chip. Unfortunately a bit too complicated to setup for testing without a PCB (at least for me).
So I hoped the DSC1001DE2-027.0000 would work too ...

Can you help me with this? What could be the reason for the test pattern not being shown?

Best regards,
Thomas

PS1: I also tried with ASSR disabled (with TEST2 high and setting the appropriate registers)

PS2: For reference, here is my current kernel log at booting:

[ 4.998385] vc4_dsi fe700000.dsi: vc4_dsi_bind ...
[ 4.998605] vc4_dsi fe700000.dsi: vc4_dsi_bind => pll_phy_clock: rate: 11718751
[ 4.998876] vc4_dsi fe700000.dsi: vc4_dsi_init_phy_clocks, parent_name: plld_dsi1 ...
[ 4.999719] vc4_dsi fe700000.dsi: vc4_dsi_bind: attach bridge ...
[ 4.999738] ti_sn65dsi86 10-002c: ti_sn_bridge_attach: start ...
[ 4.999775] vc4_dsi fe700000.dsi: mipi_dsi_device_register_full: with channel 0
[ 4.999790] mipi-dsi (null): mipi_dsi_device_alloc ...
[ 4.999950] vc4_dsi fe700000.dsi: mipi_dsi_device_register_full, done, dsi channel 0, name: ti_sn_bridge
[ 4.999965] ti_sn65dsi86 10-002c: ti_sn_bridge_attach: set dsi->lanes to 4
[ 4.999985] ti_sn65dsi86 10-002c: ti_sn_bridge_resume: start ...
[ 5.009550] ti_sn65dsi86 10-002c: ti_sn_bridge_resume: call gpiod_set_value with 1 (EN)
[ 5.021785] ti_sn65dsi86 10-002c: ti_sn_bridge_resume: done!
[ 5.022313] ti_sn65dsi86 10-002c: ti_sn_bridge_attach: clk_src is: 0 (0:= REFCLK, 1: DSI-PHY)
[ 5.022333] vc4_dsi fe700000.dsi: vc4_dsi_host_attach, channel: 0, lanes: 4 ...
[ 5.022346] ti_sn65dsi86 10-002c: ti_sn_bridge_attach: done! Attached DSI!
[ 5.022422] vc4-drm gpu: bound fe700000.dsi (ops vc4_dsi_ops [vc4])
[ 5.022781] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops [vc4])
[ 5.023320] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops [vc4])
[ 5.023605] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops [vc4])
[ 5.023856] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops [vc4])
[ 5.024055] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops [vc4])
[ 5.024305] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops [vc4])
[ 5.025319] ti_sn65dsi86 10-002c: ti_sn_bridge_suspend: start & call gpiod_set_value with 0 (EN)
[ 5.025353] ti_sn65dsi86 10-002c: ti_sn_bridge_suspend: done!
[ 5.047533] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
[ 5.053470] vc4_dsi fe700000.dsi: vc4_dsi_encoder_mode_fixup, inputs: parent_rate: 3000000091, dsi->divider: 6, mode->clock: 148500
[ 5.053489] vc4_dsi fe700000.dsi: vc4_dsi_encoder_mode_fixup => pixel_clock_hz: 148500000, pll_clock: 891000000 => divider: 3
[ 5.053503] vc4_dsi fe700000.dsi: vc4_dsi_encoder_mode_fixup => pixel_clock_hz: 166666671, mode->htotal: 2200, adjusted_mode->htotal: 2469 => adjusted_mode->clock: 166666
[ 5.053753] vc4_dsi fe700000.dsi: vc4_dsi_encoder_enable ...
[ 5.053785] vc4_dsi fe700000.dsi: vc4_dsi_encoder_enable: phy_clock: 1000002000 (pixel_clock_hz: 166666000, divider: 6)
[ 5.054894] vc4_dsi fe700000.dsi: vc4_dsi_encoder_enable: hs_clock: 1000000031 (of pll_phy_clock)
[ 5.054984] ti_sn65dsi86 10-002c: ti_sn_bridge_pre_enable: start ...
[ 5.055000] ti_sn65dsi86 10-002c: ti_sn_bridge_resume: start ...
[ 5.055106] ti_sn65dsi86 10-002c: ti_sn_bridge_resume: call gpiod_set_value with 1 (EN)
[ 5.067317] ti_sn65dsi86 10-002c: ti_sn_bridge_resume: done!
[ 5.067347] ti_sn65dsi86 10-002c: ti_sn_bridge_set_refclk_freq => use refclk lut
[ 5.067370] ti_sn65dsi86 10-002c: ti_sn_bridge_set_refclk_freq: refclk_rate: 27000000, refclk_lut[i], i: 3, found: 1
[ 5.067382] ti_sn65dsi86 10-002c: ti_sn_bridge_set_refclk_freq: set refclk_rate set reg 0x0a to 0x06 (with bitmask 14)
[ 5.092015] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: status of reg 95 (gpio configuration ): 0
[ 5.092493] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: status of reg 94 (current gpio values): 176
[ 5.125374] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: pdata->dp_lanes: 2 (max: 2)
[ 5.125395] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: set dsi lanes: set reg 0x10 to 0x00 (with bitmask 24)
[ 5.126217] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: lane assign (default 0xe4): set reg 0x59 to 0xe4
[ 5.126578] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: enhanced framing and ASSR: set reg 0x5a to 0x05
[ 5.127387] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: ASSR on/off status (bit01): 1 (0: Standard, 1: ASSR)
[ 5.127403] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: set lane polaristaion: set reg 0x5a to 0x00 (with bitmask 0xf0)
[ 5.127869] ti_sn65dsi86 10-002c: ti_sn_bridge_set_dsi_rate: bit_rate_mhz: 3984, clk_freq_mhz: 498
[ 5.128219] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: enable ASSR (driver way)
[ 5.131832] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: set DP data format: set reg 0x5b to 0x00 (0: 24bpp, 1: 18bpp)
[ 5.132308] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: set DP lane count: set reg 0x93 to 0x20 (val: 32) (2 lanes)
[ 5.141899] ti_sn65dsi86 10-002c: ti_sn_bridge_read_valid_rates: received EDP version byte: 0x2
[ 5.150891] ti_sn65dsi86 10-002c: ti_sn_bridge_calc_min_dp_rate_idx: clock: 166666 kHz, bit_rate_khz: 3999984 kHz, dp_rate_mhz: 2500 mHz => i: 4 (DP_DATA_RATE: 2700)
[ 5.150910] ti_sn65dsi86 10-002c: ti_sn_link_training: DP rate: set reg 0x94 to 0x80 (dp_rate_idx: 4)
[ 5.151707] ti_sn65dsi86 10-002c: ti_sn_link_training: enable PPL: set reg 0x0d to 0x01
[ 5.152493] ti_sn65dsi86 10-002c: ti_sn_link_training: Cursor2 0dB: set reg 0x95 to 0x00
[ 5.152838] ti_sn65dsi86 10-002c: ti_sn_link_training: start try: 0 ...
[ 5.153613] ti_sn65dsi86 10-002c: ti_sn_link_training was successfull
[ 5.153624] ti_sn65dsi86 10-002c: STATUS REGISTERS:
[ 5.154081] ti_sn65dsi86 10-002c: Status Register [0xf0] = 0x00000000
[ 5.154536] ti_sn65dsi86 10-002c: Status Register [0xf1] = 0x00000002
[ 5.154998] ti_sn65dsi86 10-002c: Status Register [0xf2] = 0x00000000
[ 5.155453] ti_sn65dsi86 10-002c: Status Register [0xf3] = 0x00000000
[ 5.155903] ti_sn65dsi86 10-002c: Status Register [0xf4] = 0x00000001
[ 5.156353] ti_sn65dsi86 10-002c: Status Register [0xf5] = 0x00000000
[ 5.156812] ti_sn65dsi86 10-002c: Status Register [0xf6] = 0x00000000
[ 5.157264] ti_sn65dsi86 10-002c: Status Register [0xf7] = 0x00000000
[ 5.157715] ti_sn65dsi86 10-002c: Status Register [0xf8] = 0x00000000
[ 5.157731] ti_sn65dsi86 10-002c: ti_sn_bridge_set_video_timings: clock: 166666, hdisplay: 1920, vdisplay: 1080, hsync_start: 2277, hsync_end: 2321, vsync_start: 1082, vsync_end: 1087
[ 5.159739] ti_sn65dsi86 10-002c: ti_sn_bridge_set_video_timings: HSYNC_PULSE_WIDTH => (val: 44) reg 2c => 2c 0
[ 5.160443] ti_sn65dsi86 10-002c: ti_sn_bridge_set_video_timings: VSYNC_PULSE_WIDTH => (val: 5) reg 30 => 5 0
[ 5.160807] ti_sn65dsi86 10-002c: ti_sn_bridge_set_video_timings: HORIZONTAL_BACK_PORCH => (val: 148) reg 34 => 0x94
[ 5.161170] ti_sn65dsi86 10-002c: ti_sn_bridge_set_video_timings: VERTICAL_BACK_PORCH => (val: 38) reg 36 => 0x26
[ 5.161524] ti_sn65dsi86 10-002c: ti_sn_bridge_set_video_timings: HORIZONTAL_FRONT_PORCH => (val: 101) reg 38 => 0x65
[ 5.161877] ti_sn65dsi86 10-002c: ti_sn_bridge_set_video_timings: VERTICAL_FRONT_PORCH => (val: 2) reg 3a => 0x2
[ 5.172427] ti_sn65dsi86 10-002c: ti_sn_bridge_test_pattern_enable: Enable Test Pattern: 0, en bits: 16
[ 5.173225] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: check refclk before enable: reg 0x0a has value 134 (refclk bits: 3, rfclk src: 0)
[ 5.173237] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: now enable video stream, update reg 0x5a with 0x0d (15 bitmask)
[ 5.174005] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: now enable the panel ...
[ 5.174017] ti_sn65dsi86 10-002c: STATUS REGISTERS:
[ 5.174470] ti_sn65dsi86 10-002c: Status Register [0xf0] = 0x00000000
[ 5.174928] ti_sn65dsi86 10-002c: Status Register [0xf1] = 0x00000002
[ 5.175379] ti_sn65dsi86 10-002c: Status Register [0xf2] = 0x00000000
[ 5.175824] ti_sn65dsi86 10-002c: Status Register [0xf3] = 0x00000000
[ 5.176271] ti_sn65dsi86 10-002c: Status Register [0xf4] = 0x00000001
[ 5.176720] ti_sn65dsi86 10-002c: Status Register [0xf5] = 0x00000000
[ 5.177165] ti_sn65dsi86 10-002c: Status Register [0xf6] = 0x00000000
[ 5.177610] ti_sn65dsi86 10-002c: Status Register [0xf7] = 0x00000000
[ 5.178057] ti_sn65dsi86 10-002c: Status Register [0xf8] = 0x00000000
[ 5.178507] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: test pattern check: reg 0x3c has value 16
[ 5.178517] ti_sn65dsi86 10-002c: ti_sn_bridge_enable: all done!

over 3 years ago

0 David (ASIC) Liu over 3 years ago

TI__Guru**** 157426 points

Hi,

Can you check and make sure the HPD is driven high?

Please see the link to this e2e FAQ, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers. You can use the spreadsheet in the FAQ to generate the DSI86 register programming values base on the sink's EDID information.

I also attached a simple 800x600 script example file, can you see if the color bar works with this example file?

1263.4DP_4DSI_RBR_800x600_Color_Bar.xml

<aardvark>
    <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1"/>
    <i2c_bitrate khz="100"/>
    
  <i2c_write addr="0x2D" count="1" radix="16">5C 01</i2c_write> <sleep ms="10"/>

   <i2c_write addr="0x2D" count="1" radix="16">FF 07</i2c_write> <sleep ms="10"/>

======DUMP CFR======
   <i2c_write addr="0x2D" count="0" radix="16">16 </i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>


   <i2c_write addr="0x2D" count="1" radix="16">16 01</i2c_write> <sleep ms="10"/>

   <i2c_write addr="0x2D" count="0" radix="16">16 </i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>

  <i2c_write addr="0x2D" count="1" radix="16">FF 00</i2c_write> <sleep ms="10"/>


======Single 4 DSI lanes======

  <i2c_write addr="0x2D" count="1" radix="16">10 26 </i2c_write> <sleep ms="10"/>

======DSI CLK FREQ======

  <i2c_write addr="0x2D" count="0" radix="16">12 </i2c_write> <sleep ms="10"/>
   <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>



======enhanced framing======

  <i2c_write addr="0x2D" count="1" radix="16">5A 04 </i2c_write> <sleep ms="10"/>


======ADDR 0x93 CFR======

   <i2c_write addr="0x2D" count="0" radix="16">93</i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="6" radix="16">00</i2c_read> <sleep ms="10"/>

======Pre0dB 1 lanes no SSC======
   <i2c_write addr="0x2D" count="1" radix="16">93 30</i2c_write> <sleep ms="10"/>

======L0mV RBR======
   <i2c_write addr="0x2D" count="1" radix="16">94 20</i2c_write> <sleep ms="10"/>

======POST2 0dB ======
   <i2c_write addr="0x2D" count="1" radix="16">95 00</i2c_write> <sleep ms="10"/>

======PLL ENABLE======
   <i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10"/>
   <i2c_write addr="0x2D" count="0" radix="16">0A</i2c_write> <sleep ms="10"/>
   <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>



======Semi-Auto TRAIN ======
   <i2c_write addr="0x2D" count="1" radix="16">96 0A</i2c_write> <sleep ms="20"/>


======ADDR 0x0A CFR======

   <i2c_write addr="0x2D" count="0" radix="16">96</i2c_write> <sleep ms="20"/>

======Read======
    <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>

=====CHA_ACTIVE_LINE_LENGTH=======
    <i2c_write addr="0x2D" count="2" radix="16">20 00 04</i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_DISPLAY_SIZE=======
    <i2c_write addr="0x2D" count="2" radix="16">24 58 02</i2c_write> <sleep ms="10"/>

=====CHA_SYNC_DELAY=======
    <i2c_write addr="0x2D" count="2" radix="16">28 00 00</i2c_write> <sleep ms="10"/>

=====CHA_HSYNC_PULSE_WIDTH=======
    <i2c_write addr="0x2D" count="2" radix="16">2C 80 80</i2c_write> <sleep ms="10"/>

=====CHA_VSYNC_PULSE_WIDTH=======
    <i2c_write addr="0x2D" count="2" radix="16">30 04 80</i2c_write> <sleep ms="10"/>

=====CHA_HORIZONTAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">34 28 </i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">36 09</i2c_write> <sleep ms="10"/>

=====CHA_HORIZONTAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">38 28</i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">3A 01</i2c_write> <sleep ms="10"/>

=====DP_18BPP_EN =======
  <i2c_write addr="0x2D" count="1" radix="16">5B 01 </i2c_write> <sleep ms="100"/>

=====COLOR BAR =======
    <i2c_write addr="0x2D" count="1" radix="16">3C 10</i2c_write> <sleep ms="100"/>

======enhanced framing and Vstream enable======

  <i2c_write addr="0x2D" count="1" radix="16">5A 0C </i2c_write> <sleep ms="100"/>

======DUMP CFR======
    <i2c_write addr="0x2D" count="0" radix="16">20</i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="32" radix="16">00</i2c_read> <sleep ms="10"/>



</aardvark>

Thanks

David

0 Thomas Mangel over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Hello David,

thanks for the quick reply.

I do not own an aardvark device. So I configured the kernel to just load the I2C bus, but not the driver.
Afterwards I run your aardvark config from a python file via a python i2c lib.

I am not quite sure if I programmed the write with count="0" correct. Perhaps you have a closer look at the resulting output ...

Unfortunately, I am still not seeing the color bars.

This is the output of the script:

<aardvark>
    <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1"/>
    <i2c_bitrate khz="100"/>
  <i2c_write addr="0x2D" count="1" radix="16">5C 01</i2c_write> <sleep ms="10"/>
      >Write 0x5c => set   1 (0x01/0b00000001)
      >Sleep: 10 ms
   <i2c_write addr="0x2D" count="1" radix="16">FF 07</i2c_write> <sleep ms="10"/>
      >Write 0xff => set   7 (0x07/0b00000111)
      >Sleep: 10 ms
======DUMP CFR======
   <i2c_write addr="0x2D" count="0" radix="16">16 </i2c_write> <sleep ms="10"/>
      >WriteByte 0x16
      >Sleep: 10 ms
======Read======
    <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>
      >Read 0x00 =>  92 (0x5c/0b01011100)
      >Sleep: 10 ms
   <i2c_write addr="0x2D" count="1" radix="16">16 01</i2c_write> <sleep ms="10"/>
      >Write 0x16 => set   1 (0x01/0b00000001)
      >Sleep: 10 ms
   <i2c_write addr="0x2D" count="0" radix="16">16 </i2c_write> <sleep ms="10"/>
      >WriteByte 0x16
      >Sleep: 10 ms
======Read======
    <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>
      >Read 2 bytes ...
      >Read nr.  0 =>   1 (0x01/0b00000001)
      >Read nr.  1 =>   0 (0x00/0b00000000)
      >Sleep: 10 ms
  <i2c_write addr="0x2D" count="1" radix="16">FF 00</i2c_write> <sleep ms="10"/>
      >Write 0xff => set   0 (0x00/0b00000000)
      >Sleep: 10 ms
======Single 4 DSI lanes======
  <i2c_write addr="0x2D" count="1" radix="16">10 26 </i2c_write> <sleep ms="10"/>
      >Write 0x10 => set  38 (0x26/0b00100110)
      >Sleep: 10 ms
======DSI CLK FREQ======
  <i2c_write addr="0x2D" count="0" radix="16">12 </i2c_write> <sleep ms="10"/>
      >WriteByte 0x12
      >Sleep: 10 ms
   <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>
      >Read 2 bytes ...
      >Read nr.  0 =>   0 (0x00/0b00000000)
      >Read nr.  1 =>   0 (0x00/0b00000000)
      >Sleep: 10 ms
======enhanced framing======
  <i2c_write addr="0x2D" count="1" radix="16">5A 04 </i2c_write> <sleep ms="10"/>
      >Write 0x5a => set   4 (0x04/0b00000100)
      >Sleep: 10 ms
======ADDR 0x93 CFR======
   <i2c_write addr="0x2D" count="0" radix="16">93</i2c_write> <sleep ms="10"/>
      >WriteByte 0x93
      >Sleep: 10 ms
======Read======
    <i2c_read addr="0x2D" count="6" radix="16">00</i2c_read> <sleep ms="10"/>
      >Read 6 bytes ...
      >Read nr.  0 =>  48 (0x30/0b00110000)
      >Read nr.  1 =>  32 (0x20/0b00100000)
      >Read nr.  2 =>   0 (0x00/0b00000000)
      >Read nr.  3 =>   0 (0x00/0b00000000)
      >Read nr.  4 =>   4 (0x04/0b00000100)
      >Read nr.  5 =>   1 (0x01/0b00000001)
      >Sleep: 10 ms
======Pre0dB 1 lanes no SSC======
   <i2c_write addr="0x2D" count="1" radix="16">93 30</i2c_write> <sleep ms="10"/>
      >Write 0x93 => set  48 (0x30/0b00110000)
      >Sleep: 10 ms
======L0mV RBR======
   <i2c_write addr="0x2D" count="1" radix="16">94 20</i2c_write> <sleep ms="10"/>
      >Write 0x94 => set  32 (0x20/0b00100000)
      >Sleep: 10 ms
======POST2 0dB ======
   <i2c_write addr="0x2D" count="1" radix="16">95 00</i2c_write> <sleep ms="10"/>
      >Write 0x95 => set   0 (0x00/0b00000000)
      >Sleep: 10 ms
======PLL ENABLE======
   <i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10"/>
      >Write 0x0d => set   1 (0x01/0b00000001)
      >Sleep: 10 ms
   <i2c_write addr="0x2D" count="0" radix="16">0A</i2c_write> <sleep ms="10"/>
      >WriteByte 0x0a
      >Sleep: 10 ms
   <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>
      >Read 2 bytes ...
      >Read nr.  0 => 134 (0x86/0b10000110)
      >Read nr.  1 =>   0 (0x00/0b00000000)
      >Sleep: 10 ms
======Semi-Auto TRAIN ======
   <i2c_write addr="0x2D" count="1" radix="16">96 0A</i2c_write> <sleep ms="20"/>
      >Write 0x96 => set  10 (0x0a/0b00001010)
      >Sleep: 20 ms
======ADDR 0x0A CFR======
   <i2c_write addr="0x2D" count="0" radix="16">96</i2c_write> <sleep ms="20"/>
      >WriteByte 0x96
      >Sleep: 20 ms
======Read======
    <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>
      >Read 0x00 =>  54 (0x36/0b00110110)
      >Sleep: 10 ms
=====CHA_ACTIVE_LINE_LENGTH=======
    <i2c_write addr="0x2D" count="2" radix="16">20 00 04</i2c_write> <sleep ms="10"/>
      >Write 0x20/0x21 => 1024
      >Write 0x20 => set   0 (0x00/0b00000000)
      >Write 0x21 => set   4 (0x04/0b00000100)
      >Sleep: 10 ms
=====CHA_VERTICAL_DISPLAY_SIZE=======
    <i2c_write addr="0x2D" count="2" radix="16">24 58 02</i2c_write> <sleep ms="10"/>
      >Write 0x24/0x25 => 600
      >Write 0x24 => set  88 (0x58/0b01011000)
      >Write 0x25 => set   2 (0x02/0b00000010)
      >Sleep: 10 ms
=====CHA_SYNC_DELAY=======
    <i2c_write addr="0x2D" count="2" radix="16">28 00 00</i2c_write> <sleep ms="10"/>
      >Write 0x28/0x29 => 0
      >Write 0x28 => set   0 (0x00/0b00000000)
      >Write 0x29 => set   0 (0x00/0b00000000)
      >Sleep: 10 ms
=====CHA_HSYNC_PULSE_WIDTH=======
    <i2c_write addr="0x2D" count="2" radix="16">2C 80 80</i2c_write> <sleep ms="10"/>
      >Write 0x2c/0x2d => 32896
      >Write 0x2c => set 128 (0x80/0b10000000)
      >Write 0x2d => set 128 (0x80/0b10000000)
      >Sleep: 10 ms
=====CHA_VSYNC_PULSE_WIDTH=======
    <i2c_write addr="0x2D" count="2" radix="16">30 04 80</i2c_write> <sleep ms="10"/>
      >Write 0x30/0x31 => 32772
      >Write 0x30 => set   4 (0x04/0b00000100)
      >Write 0x31 => set 128 (0x80/0b10000000)
      >Sleep: 10 ms
=====CHA_HORIZONTAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">34 28 </i2c_write> <sleep ms="10"/>
      >Write 0x34 => set  40 (0x28/0b00101000)
      >Sleep: 10 ms
=====CHA_VERTICAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">36 09</i2c_write> <sleep ms="10"/>
      >Write 0x36 => set   9 (0x09/0b00001001)
      >Sleep: 10 ms
=====CHA_HORIZONTAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">38 28</i2c_write> <sleep ms="10"/>
      >Write 0x38 => set  40 (0x28/0b00101000)
      >Sleep: 10 ms
=====CHA_VERTICAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">3A 01</i2c_write> <sleep ms="10"/>
      >Write 0x3a => set   1 (0x01/0b00000001)
      >Sleep: 10 ms
=====DP_18BPP_EN =======
  <i2c_write addr="0x2D" count="1" radix="16">5B 01 </i2c_write> <sleep ms="100"/>
      >Write 0x5b => set   1 (0x01/0b00000001)
      >Sleep: 100 ms
=====COLOR BAR =======
    <i2c_write addr="0x2D" count="1" radix="16">3C 10</i2c_write> <sleep ms="100"/>
      >Write 0x3c => set  16 (0x10/0b00010000)
      >Sleep: 100 ms
======enhanced framing and Vstream enable======
  <i2c_write addr="0x2D" count="1" radix="16">5A 0C </i2c_write> <sleep ms="100"/>
      >Write 0x5a => set  12 (0x0c/0b00001100)
      >Sleep: 100 ms
======DUMP CFR======
    <i2c_write addr="0x2D" count="0" radix="16">20</i2c_write> <sleep ms="10"/>
      >WriteByte 0x20
      >Sleep: 10 ms
======Read======
    <i2c_read addr="0x2D" count="32" radix="16">00</i2c_read> <sleep ms="10"/>
      >Read 32 bytes ...
      >Read nr.  0 =>   0 (0x00/0b00000000)
      >Read nr.  1 =>   4 (0x04/0b00000100)
      >Read nr.  2 =>   0 (0x00/0b00000000)
      >Read nr.  3 =>   0 (0x00/0b00000000)
      >Read nr.  4 =>  88 (0x58/0b01011000)
      >Read nr.  5 =>   2 (0x02/0b00000010)
      >Read nr.  6 =>   0 (0x00/0b00000000)
      >Read nr.  7 =>   0 (0x00/0b00000000)
      >Read nr.  8 =>   0 (0x00/0b00000000)
      >Read nr.  9 =>   0 (0x00/0b00000000)
      >Read nr. 10 =>   0 (0x00/0b00000000)
      >Read nr. 11 =>   0 (0x00/0b00000000)
      >Read nr. 12 => 128 (0x80/0b10000000)
      >Read nr. 13 => 128 (0x80/0b10000000)
      >Read nr. 14 =>   0 (0x00/0b00000000)
      >Read nr. 15 =>   0 (0x00/0b00000000)
      >Read nr. 16 =>   4 (0x04/0b00000100)
      >Read nr. 17 => 128 (0x80/0b10000000)
      >Read nr. 18 =>   0 (0x00/0b00000000)
      >Read nr. 19 =>   0 (0x00/0b00000000)
      >Read nr. 20 =>  40 (0x28/0b00101000)
      >Read nr. 21 =>   0 (0x00/0b00000000)
      >Read nr. 22 =>   9 (0x09/0b00001001)
      >Read nr. 23 =>   0 (0x00/0b00000000)
      >Read nr. 24 =>  40 (0x28/0b00101000)
      >Read nr. 25 =>   0 (0x00/0b00000000)
      >Read nr. 26 =>   1 (0x01/0b00000001)
      >Read nr. 27 =>   0 (0x00/0b00000000)
      >Read nr. 28 =>  16 (0x10/0b00010000)
      >Read nr. 29 =>   0 (0x00/0b00000000)
      >Read nr. 30 =>   0 (0x00/0b00000000)
      >Read nr. 31 =>   0 (0x00/0b00000000)
      >Sleep: 10 ms
</aardvark>

Can you see from the output what's the issue?

0 Thomas Mangel over 3 years ago in reply to Thomas Mangel

Prodigy 10 points

I just tried theaardvark config from the datasheet, but with test pattern enabled:

<configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0" />
<i2c_bitrate khz="100" />
======REFCLK 27MHz ======
<i2c_write addr="0x2D" count="1" radix="16">0A 06</i2c_write> />
======Single 4 DSI lanes======
<i2c_write addr="0x2D" count="1" radix="16">10 26</i2c_write> />
======DSIA CLK FREQ 445MHz======
<i2c_write addr="0x2D" count="1" radix="16">12 59</i2c_write> />
======enhanced framing and ASSR======
<i2c_write addr="0x2D" count="1" radix="16">5A 05</i2c_write> />
======2 DP lanes no SSC======
<i2c_write addr="0x2D" count="1" radix="16">93 20</i2c_write> />
======HBR (2.7Gbps)======
<i2c_write addr="0x2D" count="1" radix="16">94 80</i2c_write> />
======PLL ENABLE======
<i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10" />
======Verify PLL is locked======
<i2c_write addr="0x2D" count="0" radix="16">0A</i2c_write> />
<i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10" />
======POST-Cursor2 0dB ======
<i2c_write addr="0x2D" count="1" radix="16">95 00</i2c_write> />
======Write DPCD Register 0x0010A in Sink to Enable ASSR======
<i2c_write addr="0x2D" count="1" radix="16">64 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">74 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">75 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">76 0A</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">77 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">78 81</i2c_write> <sleep ms="10" />

======Semi-Auto TRAIN ======
<i2c_write addr="0x2D" count="1" radix="16">96 0A</i2c_write> <sleep ms="20" />
======Verify Training was successful======
<i2c_write addr="0x2D" count="0" radix="16">96</i2c_write> />
<i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10" />
=====CHA_ACTIVE_LINE_LENGTH is 1920 =======
<i2c_write addr="0x2D" count="2" radix="16">20 80 07</i2c_write> />
=====CHA_VERTICAL_DISPLAY_SIZE is 1080 =======
<i2c_write addr="0x2D" count="2" radix="16">24 38 04</i2c_write> />
=====CHA_HSYNC_PULSE_WIDTH is 44 positive =======
<i2c_write addr="0x2D" count="2" radix="16">2C 2C 00</i2c_write> />
=====CHA_VSYNC_PULSE_WIDTH is 5 positive=======
<i2c_write addr="0x2D" count="2" radix="16">30 05 80</i2c_write> />
=====CHA_HORIZONTAL_BACK_PORCH is 148=======
<i2c_write addr="0x2D" count="1" radix="16">34 94</i2c_write> />
=====CHA_VERTICAL_BACK_PORCH is 36=======
<i2c_write addr="0x2D" count="1" radix="16">36 24</i2c_write> />
=====CHA_HORIZONTAL_FRONT_PORCH is 88=======
<i2c_write addr="0x2D" count="1" radix="16">38 58</i2c_write> />
=====CHA_VERTICAL_FRONT_PORCH is 4=======
<i2c_write addr="0x2D" count="1" radix="16">3A 04</i2c_write> />
======DP- 24bpp======
<i2c_write addr="0x2D" count="1" radix="16">5B 00</i2c_write> />
=====COLOR BAR =======
    <i2c_write addr="0x2D" count="1" radix="16">3C 10</i2c_write> <sleep ms="100"/>


======enhanced framing, ASSR, and Vstream enable======
<i2c_write addr="0x2D" count="1" radix="16">5A 0D</i2c_write> />
</aardvark>

and it works. Hadn't expected that!

Do you see the reason it is working with that config?

0 David (ASIC) Liu over 3 years ago in reply to Thomas Mangel

TI__Guru**** 157426 points

Hi,

With the working code, if you disable the color bar, are you now able to get a picture on the screen?

Thanks

David

0 Thomas Mangel over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Hi David,

it was not that easy. I modified my display config and some parts of the linux kernel driver based on the config.
But the driver was still not able to activate the test pattern, not to speak of the real image.

Turned out that the display needs power for about a second before it accepts/processes commands. I had a P-Mosfet in the design for controlling power based on the EN signal to the bridge. Bad idea.

Afterwards there was still an issue with the display modeline and the Raspberry PI DSI kernel driver.
4 DSI lines did not work what so ever. If somebody finds a way, please contact me.

And with 3 lines, at the nominal 60Hz, the Raspberry would select a slightly too high data-rate for my 2.7 Gbps max EDP lanes (display limited). The Raspberry unfortunately uses a fixed integer divider to manipulate it's DSI reference clock. So it "overshoots" mostly quite a bit.

The solution for now was to halfen the display clock setting. The display is working with 30fps now. This is enough for my application. Might be that even 50 Hz works somehow. Will test this later.

Thanks for your help!

Best regards,
Thomas

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